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SUMMARY High Performance 32-Bit DSP--Applications in Audio, Medical, Military, Wireless Communications, Graphics, Imaging, Motor-Control, and Telephony Super Harvard Architecture--Four Independent Buses for Dual Data Fetch, Instruction Fetch, and Nonintrusive, Zero-Overhead I/O Code Compatible with All Other SHARC Family DSPs Single-Instruction-Multiple-Data (SIMD) Computational Architecture--Two 32-Bit IEEE Floating-Point Computation Units, Each with a Multiplier, ALU, Shifter, and Register File Serial Ports Offer I2S Support Via 8 Programmable and Simultaneous Receive or Transmit Pins, which Support up to 16 Transmit or 16 Receive Channels of Audio
S DSP Microcomputer ADSP-21161N
Integrated Peripherals--Integrated I/O Processor, 1M Bit On-Chip Dual-Ported SRAM, SDRAM Controller, Glueless Multiprocessing Features, and I/O Ports (Serial, Link, External Bus, SPI, and JTAG) ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and 40-Bit Floating-Point Formats KEY FEATURES 100 MHz (10 ns) Core Instruction Rate Single-Cycle Instruction Execution, Including SIMD Operations in Both Computational Units 600 MFLOPs Peak and 400 MFLOPs Sustained Performance 225-Ball 17 mm x 17 mm MBGA Package
FUNCTIONAL BLOCK DIAGRAM
CORE PROCESSOR INSTRUCTION CACHE 32 48-BIT DUAL-PORTED SRAM
BLOCK 0
TIMER
PROCESSOR PORT ADDR ADDR DATA DATA DATA
I/O PORT ADDR
BLOCK 1
TWO INDEPENDENT DUAL-PORTED BLOCKS
JTAG TEST AND EMULATION GPIO FLAGS SDRAM CONTROLLER
6
12
DATA
ADDR 8
8
DAG1 4 32
8
DAG2 4 32
PROGRAM SEQUENCER IOD 64 IOA 18
EXTERNAL PORT ADDR BUS MUX 24
32 PM ADDRESS BUS DM ADDRESS BUS 64 BUS CONNECT (PX) PM DATA BUS DM DATA BUS 64 32
MULTIPROCESSOR INTERFACE
DATA BUS MUX DATA REGISTER FILE (PEX) 16 40-BIT DATA REGISTER FILE (PEY) 16 40-BIT
32
HOST PORT
MULT
BARREL SHIFTER
BARREL SHIFTER
MULT
ALU
ALU
IOP REGISTERS (MEMORY MAPPED) CONTROL, STATUS, & DATA BUFFERS
DMA CONTROLLER SERIAL PORTS (4)
5 16 20
LINK PORTS (2) SPI PORTS (1) 4
I/O PROCESSOR
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 www.analog.com Fax:781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
ADSP-21161N
KEY FEATURES (continued) 1 M Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0, 0.5 M Bit Block 1) for Independent Access by Core Processor and DMA 200 Million Fixed-Point MACs Sustained Performance Dual Data Address Generators (DAGs) with Modulo and Bit-Reverse Addressing Zero-Overhead Looping with Single-Cycle Loop Setup, Providing Efficient Program Sequencing IEEE 1149.1 JTAG Standard Test Access Port and On-Chip Emulation Single Instruction Multiple Data (SIMD) Architecture Provides: Two Computational Processing Elements Concurrent Execution--Each Processing Element Executes the Same Instruction, but Operates on Different Data Code Compatibility--At Assembly Level, Uses the Same Instruction Set as Other SHARC DSPs Parallelism in Buses and Computational Units Enables: Single-Cycle Execution (with or without SIMD) of: a Multiply Operation, an ALU Operation, a Dual Memory Read or Write, and an Instruction Fetch Transfers Between Memory and Core at Up to Four 32-Bit Floating- or Fixed-Point Words Per Cycle, Sustained 1.6 Gbytes/s Bandwidth Accelerated FFT Butterfly Computation through a Multiply with Add and Subtract DMA Controller Supports: 14 Zero-Overhead DMA Channels for Transfers between ADSP-21161N Internal Memory and External Memory, External Peripherals, Host Processor, Serial Ports, Link Ports, or Serial Peripheral Interface (SPICompatible) 64-Bit Background DMA Transfers at Core Clock Speed, in Parallel with Full-Speed Processor Execution 800 M Bytes/s Transfer Rate over IOP Bus Host Processor Interface to 8-, 16-, and 32-Bit Microprocessors; the Host Can Directly Read/Write ADSP-21161N IOP Registers 32-Bit (or up to 48-Bit) Wide Synchronous External Port Provides: Glueless Connection to Asynchronous, SBSRAM and SDRAM External Memories Memory Interface Supports Programmable Wait State Generation and Wait Mode for Off-Chip Memory Up to 50 MHz Operation for Non-SDRAM Accesses 1:2, 1:3, 1:4, 1:6, 1:8 Clock into Core Clock Frequency Multiply Ratios 24-Bit Address, 32-Bit Data Bus. 16 Additional Data Lines via Multiplexed Link Port Data Pins Allow Complete 48-Bit Wide Data Bus for Single-Cycle External Instruction Execution Direct Reads and Writes of IOP Registers from Host or Other 21161N DSPs 62.7 Mega-Word Address Range for Off-Chip SRAM and SBSRAM Memories 32-48, 16-48, 8-48 Execution Packing for Executing Instruction Directly from 32-Bit, 16-Bit, or 8-Bit Wide External Memories 32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data Packing for DMA Transfers Directly from 32-Bit, 16-Bit, or 8-Bit Wide External Memories to and from Internal 32-, 48-, or 64-Bit Internal Memory Can be Configured to have 48-Bit Wide External Data Bus, if Link Ports are not Used. The Link Port Data Lines are Multiplexed with the Data Lines D0 to D15 and are Enabled through Control Bits in SYSCON SDRAM Controller for Glueless Interface to Low Cost External Memory Zero Wait State, 100 MHz Operation for Most Accesses Extended External Memory Banks (64 M Words) for SDRAM Accesses Page Sizes up to 2048 Words An SDRAM Controller Supports SDRAM in Any and All Memory Banks Support for Interface to Run at Core Clock and Half the Core Clock Frequency Support for 16 M Bits, 64 M Bits, 128 M Bits, and 256 M Bits with SDRAM Data Bus Configurations of 4, 8, 16, and 32 254 Mega-Word Address Range for Off-Chip SDRAM Memory Multiprocessing Support Provides: Glueless Connection for Scalable DSP Multiprocessing Architecture Distributed On-Chip Bus Arbitration for Parallel Bus Connect of Up to Six ADSP-21161Ns, Global Memory, and a Host Two 8-Bit Wide Link Ports for Point-to-Point Connectivity Between ADSP-21161Ns 400 M Bytes/s Transfer Rate over Parallel Bus 200 M Bytes/s Transfer Rate Over Link Ports Serial Ports Provide: Four 50 M Bit/s Synchronous Serial Ports with Companding Hardware 8 Bidirectional Serial Data Pins, Configurable as Either a Transmitter or Receiver I2S Support, Programmable Direction for 8 Simultaneous Receive and Transmit Channels, or Up to Either 16 Transmit Channels or 16 Receive Channels 128 Channel TDM Support for T1 and E1 Interfaces Companding Selection on a Per Channel Basis in TDM Mode Serial Peripheral Interface (SPI) Slave Serial Boot through SPI from a Master SPI Device Full-Duplex Operation Master-Slave Mode Multimaster Support Open-Drain Outputs Programmable Baud Rates, Clock Polarities and Phases 12 Programmable I/O Pins 1 Programmable Timer
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ADSP-21161N
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3 ADSP-21161N Family Core Architecture . . . . . . . . . 5 SIMD Computational Engine . . . . . . . . . . . . . . . . 5 Independent, Parallel Computation Units . . . . . . . 5 Data Register File . . . . . . . . . . . . . . . . . . . . . . . . . 5 Single-Cycle Fetch of Instruction and Four Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 5 Data Address Generators With Hardware Circular Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 5 ADSP-21161N Memory and I/O Interface Features . 5 Dual-Ported On-Chip Memory . . . . . . . . . . . . . . . 5 Off-Chip Memory and Peripherals Interface . . . . . 6 SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6 Target Board JTAG Emulator Connector . . . . . . . 7 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Peripheral (Compatible) Interface . . . . . . . . 9 Host Processor Interface . . . . . . . . . . . . . . . . . . . . 9 General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . 9 Program Booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Phase-Locked Loop and Crystal Double Enable . . 9 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Designing an Emulator-Compatible DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . 10 Additional Information . . . . . . . . . . . . . . . . . . . . . . 11 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 12 BOOT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 19 ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 19 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 20 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21 Power-up Sequencing - Silicon Revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Read - Bus Master . . . . . . . . . . . . . . . . 27 Memory Write - Bus Master . . . . . . . . . . . . . . . . 28 Synchronous Read/Write - Bus Master . . . . . . . . 29 Synchronous Read/Write - Bus Slave . . . . . . . . . . 30 Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . 31 Asynchronous Read/Write - Host to ADSP-21161N . . . . . . . . . . . . . . . . . . 33 Three-State Timing - Bus Master, Bus Slave . . . . 35 DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 37 SDRAM Interface - Bus Master . . . . . . . . . . . . . 39 Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 REV. A -3-
SPI Interface Specifications . . . . . . . . . . . . . . . . . JTAG Test Access Port and Emulation . . . . . . . . Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Enable Time . . . . . . . . . . . . . . . . . . . . . . Output Disable Time . . . . . . . . . . . . . . . . . . . . . Example System Hold Time Calculation . . . . . . . Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . Environmental Conditions . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . 225-BALL METRIC MBGA PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GENERAL DESCRIPTION
47 50 51 51 51 51 51 52 52 52 53 55 55 56
The ADSP-21161N SHARC DSP is the first low cost derivative of the ADSP-21160 featuring Analog Devices Super Harvard Architecture. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARCs in SISD (Single Instruction, Single Data) mode. Like other SHARC DSPs, the ADSP-21161N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161N includes a 100 MHz core, a dual-ported on-chip SRAM, an integrated I/O processor with multiprocessing support, and multiple internal buses to eliminate I/O bottlenecks. As was first offered in the ADSP-21160, the ADSP-21161N offers a Single-Instruction-Multiple-Data (SIMD) architecture. Using two computational units (ADSP-2106x SHARCs have one), the ADSP-21161N can double cycle performance versus the ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21161N has a 10 ns instruction cycle time. With its SIMD computational hardware running at 100 MHz, the ADSP-21161N can perform 600 million math operations per second. Table 1 shows performance benchmarks for the ADSP-21161N.
Table 1. Benchmarks (at 100 MHz) Benchmark Algorithm Speed (at 100 MHz)
1024 Point Complex FFT (Radix 4, with reversal) FIR Filter (per tap)1 IIR Filter (per biquad)1 Matrix Multiply (pipelined) [3 x 3] x [3 x 1] [4 x 4] x [4 x 1] Divide (y/x) Inverse Square Root DMA Transfers
1
171 s 5 ns 40 ns1 30 ns 37 ns 60 ns1 40 ns1 800 M bytes/s
Specified in SISD mode. Using SIMD, the same benchmark applies for two sets of computations. For example, two sets of biquad operations can be performed in the same amount of time as the SISD mode benchmark.
ADSP-21161N
The ADSP-21161N continues SHARC's industry-leading standards of integration for DSPs, combining a high performance 32-bit DSP core with integrated, on-chip system features. These features include a 1 M bit dual ported SRAM memory, host processor interface, I/O processor that supports 14 DMA channels, four serial ports, two link ports, SDRAM controller, SPI interface, external parallel bus, and glueless multiprocessing. The block diagram of the ADSP-21161N on Page 1 illustrates the following architectural features: * Two processing elements, each made up of an ALU, Multiplier, Shifter, and Data Register File * Data Address Generators (DAG1, DAG2) * Program sequencer with instruction cache * PM and DM buses capable of supporting four 32-bit data transfers between memory and the core every core processor cycle * Interval timer * On-Chip SRAM (1 M bit) * SDRAM Controller for glueless interface to SDRAMs * External port that supports: * Interfacing to off-chip memory peripherals * Glueless multiprocessing support for six ADSP21161N SHARCs * Host port read/write of IOP registers * DMA controller * Four serial ports * Two link ports * SPI compatible interface * JTAG test access port * 12 General-Purpose I/O Pins Figure 1 shows a typical single-processor system. A multiprocessing system appears in Figure 4 on Page 8.
CONTROL
ADSP-21161N
CLOCK 2 CLKIN XTAL CLK_CFG1-0 CLKDBL EBOOT LBOOT IRQ2-0 FLAG11-0 TIMEXP RPBA ID2-0 BMS
ADDRESS
DATA
CS ADDR
3 12
BRST
DATA ADDR
BOOT EPROM (OPTIONAL)
ADDR23-0
LINK DEVICES (2 MAX) (OPTIONAL) SERIAL DEVICE (OPTIONAL)
DATA47-16 RD WR LXCLK ACK LXACK MS3-0 LXDAT7-0 SCLK0 FS0 D0A D0B SCLK1 FS1 D1A D1B SCLK2 FS2 D2A D2B SCLK3 FS3 D3A D3B RAS CAS DQM SDWE SDCLK1-0 SDCKE SDA10
MEMORY DATA AND OE PERIPHERALS WE (OPTIONAL) ACK CS RAS CAS SDRAM DQM (OPTIONAL) WE CLK CKE A10 CS ADDR
SERIAL DEVICE (OPTIONAL)
SERIAL DEVICE (OPTIONAL)
DATA CLKOUT DMAR2-1 DMAG2-1
DMA DEVICE (OPTIONAL) DATA
SERIAL DEVICE (OPTIONAL)
CS HBR HBG REDY BR6-1 PA ADDR DATA
SPI COMPATIBLE DEVICE (HOST OR SLAVE) (OPTIONAL)
SPICLK SPIDS MOSI MISO
HOST PROCESSOR INTERFACE (OPTIONAL)
SBTS RESET RSTOUT JTAG 7
Figure 1. System Diagram
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ADSP-21161N
ADSP-21161N Family Core Architecture
The ADSP-21161N includes the following architectural features of the ADSP-2116x family core. The ADSP-21161N is code compatible at the assembly level with the ADSP-21160, ADSP21060, ADSP-21061, ADSP-21062, and ADSP-21065L.
SIMD Computational Engine
the processor can simultaneously fetch four operands (two over each data bus) and an instruction (from the cache), all in a single cycle.
Instruction Cache
The ADSP-21161N contains two computational processing elements that operate as a Single Instruction Multiple Data (SIMD) engine. The processing elements are referred to as PEX and PEY, and each contains an ALU, multiplier, shifter, and register file. PEX is always active, and PEY may be enabled by setting the PEYEN mode bit in the MODE1 register. When this mode is enabled, the same instruction is executed in both processing elements, but each processing element operates on different data. This architecture is efficient at executing math intensive DSP algorithms. Entering SIMD mode also has an effect on the way data is transferred between memory and the processing elements. When in SIMD mode, twice the data bandwidth is required to sustain computational operation in the processing elements. Because of this requirement, entering SIMD mode also doubles the bandwidth between memory and the processing elements. When using the DAGs to transfer data in SIMD mode, two data values are transferred with each access of memory or the register file. SIMD is supported only for internal memory accesses and is not supported for off-chip accesses.
Independent, Parallel Computation Units
The ADSP-21161N includes an on-chip instruction cache that enables three-bus operation for fetching an instruction and four data values. The cache is selective--only the instructions whose fetches conflict with PM bus data accesses are cached. This cache enables full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators With Hardware Circular Buffers
The ADSP-21161N's two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21161N contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wrap-around, reduce overhead, increase performance, and simplify implementation. Circular buffers can start and end at any memory location.
Flexible Instruction Set
Within each processing element is a set of computational units. The computational units consist of an arithmetic/logic unit (ALU), multiplier, and shifter. These units perform single-cycle instructions. The three units within each processing element are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. In SIMD mode, the parallel ALU and multiplier operations occur in both processing elements. These computation units support IEEE 32-bit single-precision floatingpoint, 40-bit extended precision floating-point, and 32-bit fixed-point data formats.
Data Register File
The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP21161N can conditionally execute a multiply, an add, and a subtract in both processing elements, while branching, all in a single instruction.
ADSP-21161N Memory and I/O Interface Features
The ADSP-21161N adds the following architectural features to the ADSP-2116x family core:
Dual-Ported On-Chip Memory
A general-purpose data register file is contained in each processing element. The register files transfer data between the computation units and the data buses, and store intermediate results. These 10-port, 32-register (16 primary, 16 secondary) register files, combined with the ADSP-2116x enhanced Harvard architecture, allow unconstrained data flow between computation units and internal memory. The registers in PEX are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data (see Figure 1 on Page 4). With the ADSP-21161N's separate program and data memory buses and on-chip instruction cache,
The ADSP-21161N contains one megabit of on-chip SRAM, organized as two blocks of 0.5 M bits. Each block can be configured for different combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor. The dualported memory in combination with three separate on-chip buses allow two data transfers from the core and one from the I/O processor, in a single cycle. On the ADSP-21161N, the memory can be configured as a maximum of 32K words of 32-bit data, 64K words of 16-bit data, 21K words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to one megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point formats is done in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and
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ADSP-21161N
PM bus, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache.
ADDRESS
ADDRESS
IOP REGISTERS LONG WORD ADDRESSING INTERNAL MEMORY SPACE NORMAL WORD ADDRESSING
0x0000 0000 - 0x0001 FFFF 0x0002 0000 - 0x0002 1FFF (BLK 0) 0x0002 8000 - 0x0002 9FFF (BLK 1) 0x0004 0000 - 0x0004 3FFF (BLK 0) 0x0005 0000 - 0x0005 3FFF (BLK 1) 0x0008 0000 - 0x0008 7FFF (BLK 0) 0x000A 0000 - 0x000A 7FFF (BLK 1)
0x0020 0000
MS0 BANK 0 0x00FF FFFF (NON-SDRAM) 0x03FF FFFF (SDRAM)
SHORT WORD ADDRESSING
0x0400 0000 IOP REGISTERS OF ADSP-21161N WITH ID = 001 IOP REGISTERS OF ADSP-21161N WITH ID = 010 0x0010 0000 - 0x0011 FFFF
0x0012 0000 - 0x0013 FFFF BANK 1
MS1
IOP REGISTERS OF ADSP-21161N WITH ID = 011
0x0014 0000 - 0x0015 FFFF
0x04FF FFFF (NON-SDRAM) 0x07FF FFFF (SDRAM)
MULTIPROCESSOR MEMORY SPACE
IOP REGISTERS OF ADSP-21161N WITH ID = 100
0x0016 0000 - 0x0017 FFFF
0x0800 0000
IOP REGISTERS OF ADSP-21161N WITH ID = 101
0x0018 0000 - 0x0019 FFFF MS2 BANK 2
IOP REGISTERS OF ADSP-21161N WITH ID = 110
0x001A 0000 - 0x001B FFFF
0x08FF FFFF (NON-SDRAM) 0x0BFF FFFF (SDRAM)
0x001C 0000 RESERVED 0x001F FFFF 0x0C00 0000
EXTERNAL MEMORY SPACE
BANK 3
MS3 0x0CFF FFFF (NON-SDRAM) 0x0FFF FFFF (SDRAM)
NOTE: BANK SIZES ARE FIXED
Figure 2. Memory Map Off-Chip Memory and Peripherals Interface
The ADSP-21161N's external port provides the processor's interface to off-chip memory and peripherals. The 62.7-M word off-chip address space (254.7-M word if all SDRAM) is included in the ADSP-21161N's unified address space. The separate onchip buses--for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data--are multiplexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus. Every access to external memory is based on an address that fetches a 32-bit word. When fetching an instruction from external memory, two 32-bit data locations are being accessed for packed instructions. Unused link port lines can also be used as additional data lines DATA15-DATA0, allowing single-cycle execution of instructions from external memory, at up to 100 MHz. Figure 3 on Page 7 shows the alignment of various accesses to external memory. -6-
The external port supports asynchronous, synchronous, and synchronous burst accesses. Synchronous burst SRAM can be interfaced gluelessly. The ADSP-21161N also can interface gluelessly to SDRAM. Addressing of external memory devices is facilitated by on-chip decoding of high-order address lines to generate memory bank select signals. The ADSP-21161N provides programmable memory wait states and external memory acknowledge controls to allow interfacing to memory and peripherals with variable access, hold, and disable time requirements.
SDRAM Interface
The SDRAM interface enables the ADSP-21161N to transfer data to and from synchronous DRAM (SDRAM) at the core clock frequency or at one-half the core clock frequency. The
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ADSP-21161N
synchronous approach, coupled with the core clock frequency, supports data transfer at a high throughput--up to 400 M bytes/s for 32-bit transfers and 600 M bytes/s for 48-bit transfers. The SDRAM interface provides a glueless interface with standard SDRAMs--16 Mb, 64 Mb, 128 Mb, and 256 Mb-- and includes options to support additional buffers between the ADSP-21161N and SDRAM. The SDRAM interface is extremely flexible and provides capability for connecting SDRAMs to any one of the ADSP-21161N's four external memory banks, with up to all four banks mapped to SDRAM. Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The ADSP-21161N supports pipelining of the address and control signals to enable such buffering between itself and multiple SDRAM devices.
Target Board JTAG Emulator Connector
Other DMA features include interrupt generation upon completion of DMA transfers, and DMA chaining for automatic linked DMA transfers.
DATA47-16 47 40 39 32 31 24 23 16 15
DATA15-0 87 L0DATA7-0 DA TA7-0 0
PROM BOOT
L1DATA7-0 DAT A15-8
8-BIT PACKED DMA D ATA 8-BIT PACKED INST RUCT ION EXECUTION 16-BIT PACKED DMA DATA 16-BIT PACKED INSTRUCTION EXECUTION F LOAT OR FIXED, D31-D0, 32-BIT PA CKED 32-BIT PA CKED INSTRUCT ION 48-BIT INSTRUCT ION FETCH (NO PACKING) NOTE: EXTRA DA TA LINES DATA15-0 AR E ONLY ACCESSIBLE IF LINK PORT S ARE DISABLED. ENAB LE THESE ADDITIONAL DATA L INKS BY SELECTING IPACK1-0 = 01 IN SYSCON.
Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21161N processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor's JTAG interface ensures that the emulator will not affect target system loading or timing. For complete information on SHARC Analog Devices DSP Tools product line of JTAG emulator operation, see the appropriate Emulator Hardware User's Guide. For detailed information on the interfacing of Analog Devices JTAG emulators with Analog Devices DSP products with JTAG emulation ports, please refer to Engineer to Engineer Note EE-68: Analog Devices JTAG Emulation Technical Reference. Both of these documents can be found on the Analog Devices website: http://www.analog.com/dsp/tech_docs.html
DMA Controller
Figure 3. External Data Alignment Options Multiprocessing
The ADSP-21161N offers powerful features tailored to multiprocessing DSP systems. The external port and link ports provide integrated glueless multiprocessing support. The external port supports a unified address space (see Figure 2 on Page 6) that enables direct interprocessor accesses of each ADSP-21161N's internal memory-mapped (I/O processor) registers. All other internal memory can be indirectly accessed via DMA transfers initiated via the programming of the IOP DMA parameter and control registers. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing up to six ADSP-21161Ns and a host processor. Master processor change over incurs only one cycle of overhead. Bus arbitration is selectable as either fixed or rotating priority. Bus lock enables indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 400 M bytes/s over the external port. Two link ports provide a second method of multiprocessing communications. Each link port can support communications to another ADSP-21161N. The ADSP-21161N, running at 100 MHz, has a maximum throughput for interprocessor communications over the links of 200 M bytes/s. The link ports and cluster multiprocessing can be used concurrently or independently.
Link Ports
The ADSP-21161N's on-chip DMA controller enables zerooverhead data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. DMA transfers can occur between the ADSP-21161N's internal memory and external memory, external peripherals, or a host processor. DMA transfers can also occur between the ADSP21161N's internal memory and its serial ports, link ports, or the SPI-compatible (Serial Peripheral Interface) port. External bus packing and unpacking of 32-, 48-, or 64-bit words in internal memory is performed during DMA transfers from either 8-, 16-, or 32-bit wide external memory. Fourteen channels of DMA are available on the ADSP-21161N--two are shared between the SPI interface and the link ports, eight via the serial ports, and four via the processor's external port (for host processor, other ADSP-21161Ns, memory, or I/O transfers). Programs can be downloaded to the ADSP-21161N using DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines (DMAR2-1, DMAG2-1).
The ADSP-21161N features two 8-bit link ports that provide additional I/O capabilities. With the capability of running at 100 MHz, each link port can support 100 M bytes/s. Link port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. The link ports can operate independently and simultaneously, with a maximum data throughput of 200 M bytes/s. Link port data is packed into 48- or 32-bit words and can be directly read by the core processor -7-
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ADSP-21161N
CLOCK RESET
ADSP-21161N #4
CONTROL ADDRESS DATA
ADSP-21161N #3
CLKIN RESET 3 ID2-0 CONTROL ADDR23-0 DATA47-16
ADSP-21161N #2
CLKIN RESET 2 ID2-0 ADDR23-0 DATA47-16 CONTROL ADDR DATA CS BOOT EPROM (OPTIONAL)
ADSP-21161N #1
BMS
CLKIN RESET 1 ID2-0
ADDR23-0 DATA47-16 RD WR ACK MS3-0 SBTS
ADDR DATA OE WE ACK CS GLOBAL MEMORY AND PERIPHERALS (OPTIONAL)
CS HBR HBG REDY ADDR BR6-2
CONTROL
CONTROL
HOST PROCESSOR INTERFACE (OPTIONAL)
DATA
ADDRESS DATA
BR1
RAS CAS DQM SDWE SDCLK1-0 SDCKE
RAS CAS DQM WE CLK CKE SDRAM (OPTIONAL)
SDA10
A10 CS
ADDR DATA
Figure 4. Shared Memory Multiprocessing System
or DMA-transferred to on-chip memory. Each link port has its own double-buffered input and output registers. Clock/acknowledge handshaking controls link port transfers. Transfers are programmable as either transmit or receive.
Serial Ports
The ADSP-21161N features four synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. Each serial port is made up of two data lines, a clock and frame sync. The data lines can be programmed to either transmit or receive.
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The serial ports operate at up to half the clock rate of the core, providing each with a maximum data rate of 50 M bit/s. The serial data pins are programmable as either a transmitter or receiver, providing greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via a dedicated DMA. Each of the serial ports features a Time Division Multiplex (TDM) multichannel mode, where two serial ports are TDM transmitters and two serial ports are TDM receivers (SPORT0 Rx paired with SPORT2 Tx, SPORT1 Rx paired with SPORT3 Tx). Each of the serial ports also support the I2S protocol (an industry standard interface commonly used by audio codecs, ADCs and DACs), with two data pins, allowing four I2S channels (using two I2S stereo devices) per serial port, with a maximum of up to 16 I2S channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For I2S mode, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional -law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated.
Serial Peripheral (Compatible) Interface Program Booting
The internal memory of the ADSP-21161N can be booted at system power-up from either an 8-bit EPROM, a host processor, the SPI interface, or through one of the link ports. Selection of the boot source is controlled by the Boot Memory Select (BMS), EBOOT (EPROM Boot), and Link/Host Boot (LBOOT) pins. 8-, 16-, or 32-bit host processors can also be used for booting.
Phase-Locked Loop and Crystal Double Enable
The ADSP-21161N uses an on-chip Phase-Locked Loop (PLL) to generate the internal clock for the core. The CLK_CFG1-0 pins are used to select ratios of 2:1, 3:1, and 4:1. In addition to the PLL ratios, the CLKDBL pin can be used for more clock ratio options. The (1x/2x CLKIN) rate set by the CLKDBL pin determines the rate of the PLL input clock and the rate at which the external port operates. With the combination of CLK_CFG1-0 and CLKDBL, ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 between the core and CLKIN are supported. See also Figure 10 on Page 20.
Power Supplies
Serial Peripheral Interface (SPI) is an industry standard synchronous serial link, enabling the ADSP-21161N SPI-compatible port to communicate with other SPI-compatible devices. SPI is a 4-wire interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21161N SPI-compatible peripheral implementation also features programmable baud rate and clock phase/polarities. The ADSP-21161N SPI-compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention.
Host Processor Interface
The ADSP-21161N has separate power supply connections for the analog (AVDD/AGND), internal (VDDINT), and external (VDDEXT) power supplies. The internal and analog supplies must meet the 1.8 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same supply. Note that the analog supply (AVDD) powers the ADSP-21161N's clock generator PLL. To produce a stable clock, provide an external circuit to filter the power input to the AVDD pin. Place the filter as close as possible to the pin. For an example circuit, see Figure 5. To prevent noise coupling, use a wide trace for the analog ground (AGND) signal and install a decoupling capacitor as close as possible to the pin.
10 VDDINT 0.1 F AGND 0.01 F AVDD
The ADSP-21161N host interface enables easy connection to standard 8-bit, 16-bit, or 32-bit microprocessor buses with little additional hardware required. The host interface is accessed through the ADSP-21161N's external port. Four channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the ADSP-21161N's external bus with the host bus request (HBR), host bus grant (HBG), and chip select (CS) signals. The host can directly read and write the internal IOP registers of the ADSP-21161N, and can access the DMA channel setup and message registers. DMA setup via a host would allow it to access any internal memory address via DMA transfers. Vector interrupt support provides efficient execution of host commands.
General-Purpose I/O Ports
Figure 5. Analog Power (AVDD) Filter Circuit Development Tools
The ADSP-21161N is supported with a complete set of software and hardware development tools, including Analog Devices emulators and VisualDSP++1 development environment. The same emulator hardware that supports other ADSP-21xxx DSPs, also fully emulates the ADSP-21161N. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder), a linker, a loader,
The ADSP-21161N also contains 12 programmable, general purpose I/O pins that can function as either input or output. As output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching.
1
VisualDSP++ is a registered trademark of Analog Devices, Inc.
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a cycle-accurate instruction-level simulator, a C/C++ compiler, and a C/C++ run-time library that includes DSP and mathematical functions. Two key points for these tools are: * Compiled ADSP-21161N C/C++ code efficiency--The compiler has been developed for efficient translation of C/C++ code to ADSP-21161N assembly. The DSP has architectural features that improve the efficiency of compiled C/C++ code. * ADSP-2106x family code compatibility--The assembler has legacy features to ease the conversion of existing ADSP-2106x applications to the ADSP-21161N. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can: * View mixed C/C++ and assembly code (interleaved source and object information) * Insert break points * Set conditional breakpoints on registers, memory, and stacks * Trace instruction execution * Perform linear or statistical profiling of program execution * Fill, dump, and graphically plot the contents of memory * Source level debugging * Create custom debugger windows The VisualDSP++ IDE lets programmers define and manage DSP software development. Its dialog boxes and property pages let programmers configure and manage all of the ADSP-21xxx development tools, including the syntax highlighting in the VisualDSP++ editor. This capability permits: * Controlling how the development tools process inputs and generate outputs. * Maintaining a one-to-one correspondence with the tool's command line switches. Analog Devices DSP emulators use the IEEE 1149.1 JTAG test access port of the ADSP-21161N processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Nonintrusive in-circuit emulation is assured by the use of the processor's JTAG interface--the emulator does not affect target system loading or timing. In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools supporting the ADSP-21xxx processor family. Hardware tools include ADSP-21xxx PC plug-in cards. Third Party software tools include DSP libraries, real-time operating systems, and block diagram design tools.
Designing an Emulator-Compatible DSP Board (Target)
uses the TAP to access the internal features of the DSP, allowing the developer to load code, set breakpoints, observe variables, observe memory, and examine registers. The DSP must be halted to send data and commands, but once an operation has been completed by the emulator, the DSP system is set running at full speed with no impact on system timing. To use these emulators, the target's design must include the interface between an Analog Devices JTAG DSP and the emulation header on a custom DSP target board.
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a 14-pin header, as shown in Figure 6. The customer must supply this header on the target board in order to communicate with the emulator. The interface consists of a standard dual row 0.025" square post header, set on 0.1" x 0.1" spacing, with a minimum post length of 0.235". Pin 3 is the key position used to prevent the pod from being inserted backwards. This pin must be clipped on the target board. Also, the clearance (length, width, and height) around the header must be considered. Leave a clearance of at least 0.15" and 0.10" around the length and width of the header, and reserve a height clearance to attach and detach the pod connector. As can be seen in Figure 6, there are two sets of signals on the header. There are the standard JTAG signals TMS, TCK, TDI, TDO, TRST, and EMU used for emulation purposes (via an emulator). There are also secondary JTAG signals BTMS, BTCK, BTDI, and BTRST that are optionally used for boardlevel (boundary scan) testing.
1 GND 3 KEY (NO PIN) 5 BTMS 7 BTCK 9 BTRST 11 BTDI 13 GND
2 EMU 4 GND 6 TMS 8 TCK 10 TRST 12 TDI 14 TDO
TOP VIEW
Figure 6. JTAG Target Board Connector for JTAG Equipped Analog Devices DSP (Jumpers in Place)
The Analog Devices DSP Tools family of emulators are tools that every DSP developer needs to test and debug hardware and software systems. Analog Devices has supplied an IEEE 1149.1 JTAG Test Access Port (TAP) on each JTAG DSP. The emulator
When the emulator is not connected to this header, place jumpers across BTMS, BTCK, BTRST, and BTDI as shown in Figure 7. This holds the JTAG signals in the correct state to allow the DSP to run free. Remove all the jumpers when connecting the emulator to the JTAG header.
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ADSP-21161N
GND 1 2 EMU
3 KEY (NO PIN) 5 BTMS 7 BTCK 9 9 11 BTDI 13
4 GND 6 TMS 8 TCK
0.88" 0.64"
BTRST
10
TRST
0.24"
12 TDI 14
Figure 8. JTAG Pod Connector Dimensions
GND
TDO
TOP VIEW
0.10"
Figure 7. JTAG Target Board Connector with No Local Boundary Scan JTAG Emulator Pod Connector
0.15"
Figure 9. JTAG Pod Connector Keep-Out Area
Figure 8 details the dimensions of the JTAG pod connector at the 14-pin target end. Figure 9 displays the keep-out area for a target board header. The keep-out area enables the pod connector to properly seat onto the target board header. This board area should contain no components (chips, resistors, capacitors, etc.). The dimensions are referenced to the center of the 0.025" square post pin.
Design-for-Emulation Circuit Information
the EE-68: Analog Devices JTAG Emulation Technical Reference on the Analog Devices website (www.analog.com)--use site search on "EE-68". This document is updated regularly to keep pace with improvements to emulator support.
Additional Information
For details on target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, and emulator pod logic, see
This data sheet provides a general overview of the ADSP-21161N architecture and functionality. For detailed information on the ADSP-2116x Family core architecture and instruction set, refer to the ADSP-21161 SHARC DSP Hardware Reference and the ADSP-21160 SHARC DSP Instruction Set Reference.
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PIN FUNCTION DESCRIPTIONS
ADSP-21161N pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST).Tie or pull unused inputs to VDDEXT or GND, except for the following: * ADDR23-0, DATA47-0, BRST, CLKOUT (Note: These pins have a logic-level hold circuit enabled on the ADSP-21161N DSP with ID2-0 = 00x.) * PA, ACK, RD, WR, DMARx, DMAGx, (ID2-0 = 00x) (Note: These pins have a pull-up enabled on the ADSP21161N DSP with ID2-0 = 00x.) * LxCLK, LxACK, LxDAT7-0 (LxPDRDE = 0) (Note: See Link Port Buffer Control Register Bit definitions in the ADSP-21161N SHARC DSP Hardware Reference.) * DxA, DxB, SCLKx, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI (Note: These pins have a pull-up.)
Table 2. Pin Function Descriptions Pin Type Function
The following symbols appear in the Type column of Table 2: A = Asynchronous, G = Ground, I = Input, O = Output, P = Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State (when SBTS is asserted or when the ADSP-21161N is a bus slave). Unlike previous SHARC processors, the ADSP-21161N contains internal series resistance equivalent to 50 on all input/output drivers except the CLKIN and XTAL pins. Therefore, for traces longer than six inches, external series resistors on control, data, clock, or frame sync pins are not required to dampen reflections from transmission line effects for point-to-point connections. However, for more complex networks such as a star configuration, series termination is still recommended.
ADDR23-0
I/O/T
DATA47-16
I/O/T
MS3-0
I/O/T
RD
I/O/T
External Bus Address. The ADSP-21161N outputs addresses for external memory and peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of other ADSP-21161Ns while all other internal memory resources can be accessed indirectly via DMA control (that is, accessing IOP DMA parameter registers). The ADSP-21161N inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. A keeper latch on the DSP's ADDR23-0 pins maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2-0=00x. External Bus Data. The ADSP-21161N inputs and outputs data and instructions on these pins. Pull-up resistors on unused data pins are not necessary. A keeper latch on the DSP's DATA47-16 pins maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2-0=00x. Note: DATA15-8 pins (multiplexed with L1DAT7-0) can also be used to extend the data bus if the link ports are disabled and will not be used. In addition, DATA7-0 pins (multiplexed with L0DAT7-0) can also be used to extend the data bus if the link ports are not used. This enables execution of 48-bit instructions from external SBSRAM (system clock speed-external port), SRAM (system clock speed-external port) and SDRAM (core clock or one-half the core clock speed). The IPACKx Instruction Packing Mode Bits in SYSCON should be set correctly (IPACK1-0=0x1) to enable this full instruction Width/No-packing Mode of operation. Memory Select Lines. These outputs are asserted (low) as chip selects for the corresponding banks of external memory. Memory bank sizes are fixed to 16 M words for nonSDRAM and 64 M words for SDRAM. The MS3-0 outputs are decoded memory address lines. In asynchronous access mode, the MS3-0 outputs transition with the other address outputs. In synchronous access modes, the MS3-0 outputs assert with the other address lines; however, they deassert after the first CLKIN cycle in which ACK is sampled asserted. In a multiprocessor system, the MSx signals are tracked by slave SHARCs. The internal addresses 24 and 25 are zeros and 26 and 27 are decoded into MS3-0. Memory Read Strobe. RD is asserted whenever ADSP-21161N reads a word from external memory or from the IOP registers of other ADSP-21161Ns. External devices, including other ADSP-21161Ns, must assert RD for reading from a word of the ADSP-21161N IOP register memory. In a multiprocessing system, RD is driven by the bus master. RD has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x.
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Table 2. Pin Function Descriptions (continued) Pin Type Function
WR
I/O/T
BRST
I/O/T
ACK
I/O/S
SBTS
I/S
CAS RAS SDWE DQM SDCLK0 SDCLK1
I/O/T I/O/T I/O/T O/T I/O/S/T O/S/T
SDCKE SDA10
I/O/T O/T
IRQ2-0 FLAG11-0 TIMEXP HBR
I/A I/O/A O I/A
Memory Write Low Strobe. WR is asserted when ADSP-21161N writes a word to external memory or IOP registers of other ADSP-21161Ns. External devices must assert WR for writing to ADSP-21161N IOP registers. In a multiprocessing system, the bus master drives WR. WR has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. Sequential Burst Access. BRST is asserted by ADSP-21161N to indicate that data associated with consecutive addresses is being read or written. A slave device samples the initial address and increments an internal address counter after each transfer. The incremented address is not pipelined on the bus. A master ADSP-21161N in a multiprocessor environment can read slave external port buffers (EPBx) using the burst protocol. BRST is asserted after the initial access of a burst transfer. It is asserted for every cycle after that, except for the last data request cycle (denoted by RD or WR asserted and BRST negated). A keeper latch on the DSP's BRST pin maintains the input at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2-0=00x. Memory Acknowledge. External devices can de-assert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-21161N deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. ACK has a 20 k internal pull-up resistor that is enabled during reset or on DSPs with ID2-0=00x. Suspend Bus and Three-State. External devices can assert SBTS (low) to place the external bus address, data, selects, and strobes in a high impedance state for the following cycle. If the ADSP-21161N attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21161N deadlock. SDRAM Column Access Strobe. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDRAM Row Access Strobe. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command and during SDRAM power-up initialization. SDRAM Clock Output 0. Clock for SDRAM devices. SDRAM Clock Output 1. Additional clock for SDRAM devices. For systems with multiple SDRAM devices, handles the increased clock load requirements, eliminating need of offchip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with the SDRAM device. SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a nonSDRAM accesses or host accesses. This pin replaces the DSP's A10 pin only during SDRAM accesses. Interrupt Request Lines. These are sampled on the rising edge of CLKIN and may be either edge-triggered or level-sensitive. Flag Pins. Each is configured via control bits as either an input or output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. Timer Expired. Asserted for four core clock cycles when the timer is enabled and TCOUNT decrements to zero. Host Bus Request. Must be asserted by a host processor to request control of the ADSP21161N's external bus. When HBR is asserted in a multiprocessing system, the ADSP21161N that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21161N places the address, data, select, and strobe lines in a high impedance state. HBR has priority over all ADSP-21161N bus requests (BR6-1) in a multiprocessing system.
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Table 2. Pin Function Descriptions (continued) Pin Type Function
HBG
I/O
CS REDY DMAR1
I/A O (O/D) I/A
DMAR2
I/A
DMAG1
O/T
DMAG2
O/T
BR6-1
I/O/S
BMSTR
O
ID2-0
I
RPBA
I/S
PA
I/O/T
DxA
I/O
DxB
I/O
SCLKx
I/O
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted (held low) by the ADSP-21161N until HBR is released. In a multiprocessing system, HBG is output by the ADSP-21161N bus master and is monitored by all others. After HBR is asserted, and before HBG is given, HBG will float for 1 tCK (1 CLKIN cycle). To avoid erroneous grants, HBG should be pulled up with a 20k to 50k external resistor. Chip Select. Asserted by host processor to select the ADSP-21161N. Host Bus Acknowledge. The ADSP-21161N deasserts REDY (low) to add wait states to a host access of its IOP registers when CS and HBR inputs are asserted. DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. DMA Grant 1 (DMA Channel 11). Asserted by ADSP-21161N to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG1 has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21161N to indicate that the requested DMA starts on the next cycle. Driven by bus master only. DMAG2 has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. Multiprocessing Bus Requests. Used by multiprocessing ADSP-21161Ns to arbitrate for bus mastership. An ADSP-21161N only drives its own BRx line (corresponding to the value of its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-21161Ns, the unused BRx pins should be pulled high; the processor's own BRx line must not be pulled high or low because it is an output. Bus Master Output. In a multiprocessor system, indicates whether the ADSP-21161N is current bus master of the shared external bus. The ADSP-21161N drives BMSTR high only while it is the bus master. In a single-processor system (ID=000), the processor drives this pin high. This pin is used for debugging purposes. Multiprocessing ID. Determines which multiprocessing bus request (BR6-BR1) is used by ADSP-21161N. ID= 001 corresponds to BR1, ID=010 corresponds to BR2, and so on. Use ID=000 or ID=001 in single-processor systems. These lines are a system configuration selection that should be hardwired or only changed at reset. Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This signal is a system configuration selection that must be set to the same value on every ADSP21161N. If the value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on every ADSP-21161N. Priority Access. Asserting its PA pin enables an ADSP-21161N bus slave to interrupt background DMA transfers and gain access to the external bus. PA is connected to all ADSP21161Ns in the system. If access priority is not required in a system, the PA pin should be left unconnected. PA has a 20 k internal pull-up resistor that is enabled for DSPs with ID2-0=00x. Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data. Transmit/Receive Serial Clock (Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal pull-up resistor. This signal can be either internally or externally generated.
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Table 2. Pin Function Descriptions (continued) Pin Type Function
FSx
I/O
SPICLK
I/O
SPIDS
I
MOSI
I/O (o/d)
MISO
I/O (o/d)
LxDAT7-0 [DATA15-0]
I/O [I/O/T]
LxCLK LxACK EBOOT LBOOT
I/O I/O I I
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data. This signal is either generated internally or externally. It can be active high or low or an early or a late frame sync, in reference to the shifting of serial data. Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is transferred. The master may transmit data at a variety of baud rates. SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. Clock polarity and clock phase relative to data are programmable into the SPICTL control register and define the transfer format. SPICLK has a 50 k internal pull-up resistor. Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This input signal behaves like a chip select, and is provided by the master device for the slave devices. In multimaster mode SPIDS signal can be asserted to a master device to signal that an error has occurred, as some other device is also trying to be the master device. If asserted low when the device is in master mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where FLAG3-0 are used, this pin must be tied or pulled high to VDDEXT on the master device. For ADSP-21161N to ADSP21161N SPI interaction, any of the master ADSP-21161N's FLAG3-0 pins can be used to drive the SPIDS signal on the ADSP-21161N SPI slave device. SPI Master Out Slave. If the ADSP-21161N is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21161N is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data. In an ADSP-21161N SPI interconnection, the data is shifted out from the MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal pullup resistor. SPI Master In Slave Out. If the ADSP-21161N is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21161N is configured as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In an ADSP-21161N SPI interconnection, the data is shifted out from the MISO output pin of the slave and shifted into the MISO input pin of the master. MISO has an internal pullup resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register. Note: Only one slave is allowed to transmit data at any given time. Link Port Data (Link Ports 0-1). For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when used as a data pin; or a 20 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 k internal pull-down resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. Note: L1DAT7-0 are multiplexed with the DATA15-8 pins L0DAT7-0 are multiplexed with the DATA7-0 pins. If link ports are disabled and are not used, these pins can be used as additional data lines for executing instructions at up to the full clock rate from external memory. See DATA47-16 for more information. Link Port Clock (Link Ports 0-1). Each LxCLK pin has an internal pull-down 50 k resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. Link Port Acknowledge (Link Ports 0-1). Each LxACK pin has an internal pull-down 50 k resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register. EPROM Boot Select. For a description of how this pin operates, see the table in the BMS pin description. This signal is a system configuration selection that should be hardwired. Link Boot. For a description of how this pin operates, see the table in the BMS pin description. This signal is a system configuration selection that should be hardwired.
REV. A
-15-
ADSP-21161N
Table 2. Pin Function Descriptions (continued) Pin Type Function
BMS
I/O/T
CLKIN
I
XTAL CLK_CFG1-0
O I
CLKDBL
I
CLKOUT
O/T
RESET
I/A
Boot Memory Select. Serves as an output or input as selected with the EBOOT and LBOOT pins (see Table 4). This input is a system configuration selection that should be hardwired. For Host and PROM boot, DMA channel 10 (EPB0) is used. For Link boot and SPI boot, DMA channel 8 is used. Three-state only in EPROM boot mode (when BMS is an output). Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21161N clock input. It configures the ADSP-21161N to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21161N to use the external clock source such as an external clock oscillator.The ADSP-21161N external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple of the CLKIN frequency; it is programmable at powerup via the CLK_CFG1-0 pins. CLKIN may not be halted, changed, or operated below the specified frequency. Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the ADSP21161N's internal clock oscillator or to disable it to use an external clock source. See CLKIN. Core/CLKIN Ratio Control. ADSP-21161N core clock (instruction cycle) rate is equal to n x PLLICLK where n is user selectable to 2, 3, or 4, using the CLK_CFG1-0 inputs. These pins can also be used in combination with the CLKDBL pin to generate additional core clock rates of 6 x CLKIN and 8 x CLKIN (see the Clock Rate Ratios table in the CLKDBL description). Crystal Double Mode Enable. This pin is used to enable the 2x clock double circuitry, where CLKOUT can be configured as either 1x or 2x the rate of CLKIN. This CLKIN double circuit is primarily intended to be used for an external crystal in conjunction with the internal clock generator and the XTAL pin. The internal clock generator when used in conjunction with the XTAL pin and an external crystal is designed to support up to a maximum of 25 MHz external crystal frequency. CLKDBL can be used in XTAL mode to generate a 50 MHz input into the PLL. The 2x clock mode is enabled (during RESET low) by tying CLKDBL to GND, otherwise it is connected to VDDEXT for 1x clock mode. For example, this enables the use of a 25 MHz crystal to enable 100 MHz core clock rates and a 50 MHz CLKOUT operation when CLK_CFG0=0, CLK_CFG1=0 and CLKDBL=0. This pin can also be used to generate different clock rate ratios for external clock oscillators as well. The possible clock rate ratio options (up to 100 MHz) for either CLKIN (external clock oscillator) or XTAL (crystal input) are shown in Table 3 on Page 17. An 8:1 ratio enables the use of a 12.5 MHz crystal to generate a 100 MHz core (instruction clock) rate and a 25 MHz CLKOUT (external port) clock rate. See also Figure 10 on Page 20. Note: When using an external crystal, the maximum crystal frequency cannot exceed 25 MHz. For all other external clock sources, the maximum CLKIN frequency is 50 MHz. Local Clock Out. CLKOUT is 1x or 2x and is driven at either 1x or 2x the frequency of CLKIN frequency by the current bus master. The frequency is determined by the CLKDBL pin. This output is three-stated when the ADSP-21161N is not the bus master or when the host controls the bus (HBG asserted). A keeper latch on the DSP's CLKOUT pin maintains the output at the level it was last driven. This latch is only enabled on the ADSP-21161N with ID2-0=00x. If CLKDBL enabled, CLKOUT=2 x CLKIN If CLKDBL disabled, CLKOUT=1 x CLKIN Note: CLKOUT is only controlled by the CLKDBL pin and operates at either 1 x CLKIN or 2 x CLKIN. Do not use CLKOUT in multiprocessing systems. Use CLKIN instead. Processor Reset. Resets the ADSP-21161N to a known state and begins execution at the program memory location specified by the hardware reset vector address. The RESET input must be asserted (low) at power-up.
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REV. A
ADSP-21161N
Table 2. Pin Function Descriptions (continued) Pin Type Function
RSTOUT1
O
TCK TMS TDI TDO TRST
I I/S I/S O I/A
EMU
O (O/D)
VDDINT VDDEXT AVDD
P P P
AGND GND NC
1 2
G G
Reset Out. When RSTOUT is asserted (low), this pin indicates that the core blocks are in reset. It is deasserted 4080 cycles after RESET is deasserted indicating that the PLL is stable and locked. Test Clock (JTAG). Provides a clock for JTAG boundary scan. Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 k internal pull-up resistor. Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 k internal pull-up resistor. Test Data Output (JTAG). Serial scan output of the boundary scan path. Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the ADSP-21161N. TRST has a 20 k internal pull-up resistor. Emulation Status. Must be connected to the ADSP-21161N Analog Devices DSP Tools product line of JTAG emulators target board connector only. EMU has a 50 k internal pull-up resistor. Core Power Supply. Nominally +1.8 V dc and supplies the DSP's core processor (14 pins). I/O Power Supply. Nominally +3.3 V dc. (13 pins). Analog Power Supply. Nominally +1.8 V dc and supplies the DSP's internal PLL (clock generator). This pin has the same specifications as VDDINT, except that added filtering circuitry is required. See Power Supplies on Page 9. Analog Power Supply Return. Power Supply Return. (26 pins). Do Not Connect. Reserved pins that must be left open and unconnected. (5 pins2).
RSTOUT exists only for silicon revision 1.2. Four NC pins for silicon revision 1.2, because RSTOUT has been added.
Table 3. Clock Rate Ratios CLKDBL CLK_CFG1 CLK_CFG0 Core:CLKIN CLKIN:CLKOUT
1 1 1 0 0 0
BOOT MODES
0 0 1 0 0 1
0 1 0 0 1 0
2:1 3:1 4:1 4:1 6:1 8:1
1:1 1:1 1:1 1:2 1:2 1:2
Table 4. Boot Mode Selection EBOOT LBOOT BMS Booting Mode
1 0 0 0 0 1
0 0 1 1 0 1
Output 1 (Input) 0 (Input) 1 (Input) 0 (Input) x (Input)
EPROM (Connect BMS to EPROM chip select.) Host Processor Serial Boot via SPI Link Port No Booting. Processor executes from external memory. Reserved
REV. A
-17-
ADSP-21161N
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter Test Conditions Min C Grade Max Min K Grade Max Unit
VDDINT AVDD VDDEXT VIH VIL TCASE
1
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage1 @ VDDEXT = max Low Level Input Voltage1 @ VDDEXT = min Case Operating Temperature2
1.71 1.71 3.13 2.0 -0.5 -40
1.89 1.89 3.47 VDDEXT +0.5 +0.8 +105
1.71 1.71 3.13 2.0 -0.5 0
1.89 1.89 3.47 VDDEXT +0.5 +0.8 +85
V V V V V C
Specifications subject to change without notice. Applies to input and bidirectional pins: DATA47-16, ADDR23-0, MS3-0, RD, WR, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, HBR, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, CLKIN, RESET, TRST, TCK, TMS, TDI. 2 See Thermal Characteristics on Page 52 for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Min
2
Max
Unit
VOH VOL IIH IIL IIHC IILC IIKH IIKL IIKH-OD IIKL-OD IILPU IOZH IOZL IOZLPU1 IOZLPU2 IOZHPD1 IOZHPD2 IDD-INPEAK IDD-INHIGH IDD-INLOW IDD-IDLE AIDD CIN
1
High Level Output Voltage Low Level Output Voltage1 High Level Input Current3, 4 Low Level Input Current3 CLKIN High Level Input Current5 CLKIN Low Level Input Current5 Keeper High Load Current6 Keeper Low Load Current6 Keeper High Overdrive Current6, 7, 8 Keeper Low Overdrive Current6, 7, 8 Low Level Input Current Pull-Up4 Three-State Leakage Current9, 10, 11 Three-State Leakage Current9, 12, 13 Three-State Leakage Current Pull-Up110 Three-State Leakage Current Pull-Up211 Three-State Leakage Current Pull-Down112 Three-State Leakage Current Pull-Down213 Supply Current (Internal)14, 15 Supply Current (Internal)15, 16 Supply Current (Internal)15, 17 Supply Current (Idle)15, 18 Supply Current (Analog)19 Input Capacitance20, 21
1
@ VDDEXT = min, IOH = -2.0 mA @ VDDEXT = min, IOL = 4.0 mA2 @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 2.0 V @ VDDEXT = max, VIN = 0.8 V @ VDDEXT = max @ VDDEXT = max @ VDDEXT = max, VIN = 0 V @ VDDEXT= max, VIN = VDDEXT max @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = 0 V @ VDDEXT = max, VIN = VDDEXT max @ VDDEXT = max, VIN = VDDEXT max tCCLK = 10.0 ns, VDDINT = max tCCLK = 10.0 ns, VDDINT = max tCCLK = 10.0 ns, VDDINT = max tCCLK = 10.0 ns, VDDINT = max @ AVDD = max fIN = 1 MHz, TCASE = 25C, VIN = 1.8 V
2.4 0.4 10 10 35 35 -100 200
-250 50 -300 300
350 10 10 500 350 350 500 900 650 500 400 10 4.7
V V A A A A A A A A A A A A A A A mA mA mA mA mA pF
Specifications subject to change without notice. Applies to output and bidirectional pins: DATA47-16, ADDR23-0, MS3-0, RD, WR, ACK, DQM, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR6-1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL, TDO, CLKOUT, TIMEXP, RSTOUT. 2 See Output Drive Currents on Page 51 for typical drive current capabilities. 3 Applies to input pins: DATA47-16, ADDR23-0, MS3-0, SBTS, IRQ2-0, FLAG11-0, HBG, HBR, CS, BR6-1, ID2-0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDCLK0, LxDAT7-0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN. 4 Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI. 5 Applies to CLKIN only. 6 Applies to all pins with keeper latches: ADDR23-0, DATA47-0, MS3-0, BRST, CLKOUT. 7 Current required to switch from kept high to low or from kept low to high. 8 Characterized, but not tested.
-18-
REV. A
ADSP-21161N
Applies to three-statable pins: DATA47-16, ADDR23-0, MS3-0, CLKOUT, FLAG11-0, REDY, HBG, BMS, BR6-1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10, BRST. 10 Applies to three-statable pins with 20 k pull-ups: RD, WR, DMAG1, DMAG2, PA. 11 Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI 12 Applies to three-statable pins with 50 k internal pull-downs: LxDAT7-0 (below Revision1.2), LxCLK, LxACK. Use IOZHPD2 for Rev. 1.2 and higher. 13 Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher). 14 The test program used to measure IDDINPEAK represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. For more information, see "Power Dissipation" on Page 21. 15 Current numbers are for VDDINT and AVDD supplies combined. 16 IDDINHIGH is a composite average based on a range of high activity code. See Power Dissipation on Page 21. 17 IDDINLOW is a composite average based on a range of low activity code. See Power Dissipation on Page 21. 18 Idle denotes ADSP-21161N state during execution of IDLE instruction. See Power Dissipation on Page 21. 19 Characterized, but not tested. 20 Applies to all signal pins. 21 Guaranteed, but not tested.
9
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDDINT)1 . . -0.3 V to +2.2 V Analog (PLL) Supply Voltage (AVDD)1 . . . . -0.3 V to +2.2 V External (I/O) Supply Voltage (VDDEXT)1 . . -0.3 V to +4.6 V Input Voltage1 . . . . . . . . . . . . . . . . -0.5 V to VDDEXT + 0.5 V Output Voltage Swing1 . . . . . . . . . -0.5 V to VDDEXT + 0.5 V Load Capacitance1 . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF Storage Temperature Range1 . . . . . . . . . . .-65C to +150C
1
Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITY
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21161N features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
-19-
ADSP-21161N TIMING SPECIFICATIONS
The ADSP-21161N's internal clock switches at higher frequencies than the system input clock (CLKIN). To generate the internal clock, the DSP uses an internal phase-locked loop (PLL). This PLL-based clocking minimizes the skew between the system clock (CLKIN) signal and the DSP's internal clock (the clock source for the external port logic and I/O pads). The ADSP-21161N's internal clock (a multiple of CLKIN) provides the clock signal for timing internal memory, processor core, link ports, serial ports, and external port (as required for read/write strobes in asynchronous access mode). During reset, program the ratio between the DSP's internal clock frequency and external (CLKIN) clock frequency with the CLK_CFG1-0
Table 5. CLKOUT and CCLK Clock Generation Operation Timing Requirements Description1 Calculation
and CLKDBL pins. Even though the internal clock is the clock source for the external port, it behaves as described in the Clock Rate Ratio chart in Table 3 on Page 17. To determine switching frequencies for the serial and link ports, divide down the internal clock, using the programmable divider control of each port (DIVx for the serial ports and LxCLKD for the link ports). Note the following definitions of various clock periods that are a function of CLKIN and the appropriate ratio control. Figure 10 enables Core-to-CLKIN ratios of 2:1, 3:1, 4:1, 6:1, and 8:1 with external oscillator or crystal. It also shows support for CLKOUT-to-CLKIN ratios of 1:1 and 2:1.
CLKIN CLKOUT PLLICLK CCLK tCK tCCLK tLCLK tSCLK tSDK tSPICLK
1
Input Clock External Port System Clock PLL Input Clock Core Clock CLKIN Clock Period (Processor) Core Clock Period Link Port Clock Period Serial Port Clock Period SDRAM Clock Period SPI Clock Period
1/tCK 1/tCKOP 1/tPLLIN 1/tCCLK 1/CLKIN 1/CCLK (tCCLK) x LR (tCCLK) x SR (tCCLK) x SDCKR (tCCLK) x SPIR
where: LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD) SR = serial port-to-core clock ratio (wide range, determined by CLKDIV) SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register) SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register) LCLK = Link Port Clock SCLK = Serial Port Clock SDK = SDRAM Clock SPICLK = SPI Clock
SYNCHRONOUS EP MULTIPROCESSING SBSRAM
ASYNCHRONOUS EP HOST SRAM
PLLICLK (4.2-50MHz)
HARDWARE INTERRUPT I/O FLAG TIMER
CCLK (33.3-100MHz)
CORE I/O PROCESSOR
1,
LINK PORTS 1/2, 1/3, 1/4
CLKIN (CRYSTAL OSCILLATOR 4.2-50MHz) CLOCK DOUBLER 1, 2 XTAL (QUARTZ CRYSTAL 25MHz MAX) CLKDBL
SDRAM 1, 1/2
RATIOS 2, 3, 4 PLL
SERIAL PORTS 1/2 MAX
SPI 1/8 MAX
CLKOUT
CLK_CFG1-0
Figure 10. Core Clock and System Clock Relationship to CLKIN
-20-
REV. A
ADSP-21161N
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, it is not meaningful to add parameters to derive longer times. See Figure 40 on Page 51 under Test Conditions for voltage reference levels. Switching characteristics specify how the processor changes its signals. Circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics describe what the processor will do in a given circumstance. Use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices.
Table 6. Operation Types Versus Input Current Operation Peak Activity1 (IDDINPEAK) High Activity1 (IDDINHIGH) Low Activity1 (IDDINLOW) Power Dissipation
Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation depends on the instruction execution sequence and the data operands involved. Using the current specifications (IDDINPEAK, IDDINHIGH, IDDINLOW, IDDIDLE) from the Electrical Characteristics on Page 18 and the current-versusoperation information in Table 6, the programmer can estimate the ADSP-21161N's internal power supply (VDDINT) input current for a specific application, according to the following formula:
% Peak x I DDINPEAK % High x I DDINHIGH % Low x I DDINLOW + % Idle x I DDIDLE -------------------------------------------------I DDINT
Instruction Type Instruction Fetch Core Memory Access2 Internal Memory DMA External Memory DMA Data bit pattern for core memory access and DMA
1 2
Multifunction Cache 2 per tCK cycle (DMx64 and PMx64) 1 per 2 tCCLK cycles 1 per external port cycle (x32) Worst case
Multifunction Internal Memory 1 per tCK cycle (DMx64) 1 per 2 tCCLK cycles 1 per external port cycle (x32) Random
Single Function Internal Memory None N/A N/A N/A
The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations. These assume a 2:1 core clock ratio. For more information on ratios and clocks (tCK and tCCLK), see the timing ratio definitions on Page 20.
The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: * The number of output pins that switch during each cycle (O) * The maximum frequency at which they can switch (f) * Their load capacitance (C) * Their voltage swing (VDD) and is calculated by:
P EXT = O x C x V DD x f
2
* External Data Memory writes can occur every cycle at a rate of 1/tCK with 50% of the pins switching * The bus cycle time is 50 MHz * The external SDRAM clock rate is 100 MHz * Ignoring SDRAM refresh cycles * Addresses are incremental and on the same page The PEXT equation is calculated for each class of pins that can drive, as shown in Table 7. A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation:
P TOTAL = P EXT + P INT + P PLL
The load capacitance should include the processor package capacitance (CIN). The switching frequency includes driving the load high and then back low. At a maximum rate of 1/tCK, address and data pins can drive high and low, while writing to a SDRAM memory. Example: Estimate PEXT with the following assumptions: * A system with one bank of external memory (32 bit) * Two 1M 16 SDRAM chips are used, each with a load of 10 pF (ignoring trace capacitance)
Where: PEXT is from Table 7. PINT is IDDINT x 1.8 V, using the calculation IDDINT listed in Power Dissipation on Page 21. PPLL is AIDD x 1.8 V, using the value for AIDD listed in the Electrical Characteristics on Page 18.
REV. A
-21-
ADSP-21161N
Table 7. External Power Calculations (3.3 V Device) Pin Type Number of Pins % Switching C f VDD2 = PEXT
Address MSx SDWE Data SDCLK0
11 4 1 32 1
20 0 0 50 100
24.7 pF 24.7 pF 24.7 pF 14.7 pF 24.7 pF
50 MHz N/A N/A 50 MHz 100 MHz
10.9 V 10.9 V 10.9 V 10.9 V 10.9 V
= 0.030 W = 0.000 W = 0.000 W = 0.128 W = 0.027 W PEXT = 0.185 W
Note that the conditions causing a worst-case PEXT are different from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones to all zeros. Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously.
Power-Up Sequencing - Silicon Revision 0.3, 1.0, 1.1
The timing requirements for DSP startup for silicon revision 0.3, 1.0, or 1.1 are given in Table 8.
Table 8. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup) Parameter Min Max Unit
Timing Requirements tRSTVDD tVDDRAMP tIVDDEVDD tCLKVDD tVDDRST tCLKRST tPLLRST
1
RESET Low Before VDDINT/VDDEXT on VDDINT/VDDEXT Voltage Ramp Rate1 VDDINT on Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid VDDINT/VDDEXT Valid Before RESET Deasserted2 CLKIN Valid Before RESET Deasserted3 PLL Control Setup Before RESET Deasserted
0 0.0009 -50 0 100 100 20
9 +200 200
ns V/s ms ms s s s
The minimum 0.9 V/ms is based on the slowest allowable ramp-up time (2 ms) for VDDINT to ramp from 0 volts to 1.8 volts and (3.6 ms) for VDDEXT to ramp from 0 volts to 3.3 volts. 2 The minimum time of 0 ns assumes that VDDINT and VDDEXT power supplies are valid. The VDDINT and VDDEXT supplies must be fully ramped to their 1.8 and 3.3 volt rails before RESET can be deasserted. 3 The 100 s minimum assumes a stable CLKIN signal after meeting worst-case start-up timing of crystal oscillator circuits. Refer to the crystal oscillator manufacturer's data sheet for start-up time. A 25 ms maximum oscillator start-up time can be assumed if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 100 s is the minimum time required for the PLL to reliably lock to a valid (stable) CLKIN frequency.
RESET
tRSTVDD
VDDINT
tVDDRST
tVDDRAMP tVDDRAMP
VDDEXT
tIVDDEVDD tCLKVDD
CLKIN
tCLKRST
CLKDBL CLK_CFG1-0
tPLLRST
Figure 11. Power-Up Sequencing for Revisions 0.3, 1.0, and 1.1 (DSP Startup)
-22-
REV. A
ADSP-21161N
Power-Up Sequencing - Silicon Revision 1.2
The timing requirements for DSP startup for silicon with revision 1.2 are given in Table 9.
Table 9. Power-Up Sequencing for Revision 1.2 (DSP Startup) Parameter Min Max Unit
Timing Requirements tRSTVDD RESET Low Before VDDINT/VDDEXT on tIVDDEVDD VDDINT on Before VDDEXT CLKIN Valid After VDDINT/VDDEXT Valid1 tCLKVDD tCLKRST CLKIN Valid Before RESET Deasserted2 tPLLRST PLL Control Setup Before RESET Deasserted3 tWRST Subsequent RESET Low Pulsewidth4 Switching Requirements tCORERST DSP core reset deasserted after RESET deasserted
1
0 -50 0 10 20 4tCK 4080tCK3, 5
+200 200
ns ms ms s s ns
Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem. 2 Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time. Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal. 3 Based on CLKIN cycles 4 Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I/O pins. 5 The 4080 cycle count depends on tSRST specification in Table 11. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in 4081 cycles maximum.
RSTOUT does not currently exist for ADSP-21161N revisions 0.3, 1.0, and 1.1. This new signal will be placed on one of the current no-connect pins: ball B15.
RESET
tRSTVDD
VDDINT
tIVDDEVDD
VDDEXT
tCLKRST tCLKVDD
CLKIN
CLKDBL CLK_CFG1-0
tPLLRST
RSTOUT
tCORERST
Figure 12. Power-Up Sequencing for Revision 1.2 (DSP Startup)
During the power-up sequence of the DSP, differences in the ramp-up rates and activation time between the two supplies can cause current to flow in the I/O ESD protection circuitry. To prevent damage to the ESD diode protection circuitry, Analog Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V and 3.3 V power supplies as shown in Figure 13. It protects the ADSP-21161N from partially powering the 3.3 V supply. Including a Schottky diode will shorten the delay between the supply ramps and thus prevent damage to the ESD diode
REV. A
-23-
ADSP-21161N
protection circuitry. With this technique, if the 1.8 V rail rises ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail along with the 1.8 V rail.
Clock Input
DC INPUT SOURCE 3.3V I/O VOLTAGE REGULATOR VDDEXT
ADSP-21161N
In systems that use multiprocessing or SBSRAM, CLKDBL cannot be enabled nor can the systems use an external crystal as the CLKIN source. Do not use CLKOUT as the clock source for the SBSRAM device. Using an external crystal in conjunction with CLKDBL to generate a CLKOUT frequency is not supported. Negative hold times can result from the potential skew between CLKIN and CLKOUT.
Table 10. Clock Input
1.8V CORE VOLTAGE REGULATOR
VDDINT
Figure 13. Dual Voltage Schottky Diode
100 MHz Parameter Min Max Unit
Timing Requirements tCK CLKIN Period1 tCKL CLKIN Width Low1 tCKH CLKIN Width High1 CLKIN Rise/Fall (0.4 V-2.0 V) tCKRF tCCLK CCLK Period Switching Characteristics tDCKOO CLKOUT Delay After CLKIN tCKOP CLKOUT Period tCKWH CLKOUT Width High tCKWL CLKOUT Width Low
1
20 7.5 7.5 10 0 tCKOP -1 tCKOP/2-2 tCKOP/2-2
238 119 119 3 30 2 tCKOP +1 tCKOP/2+2 tCKOP/2+2
ns ns ns ns ns ns ns ns ns
CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired tCCLK.
tCK
CLKIN
the necessary components to CLKIN and XTAL. Figure 15 shows the component connections used for a crystal operating in fundamental mode.
tCKH tDCKOO
1
tCKL tCKOP1
CLKIN XTAL
tCKWH1
CLKOUT
tCKWL1
C1 27pF X1 C2 27pF
tDCKOO2 tDCKOO2 tCKWH
CLKOUT NOTES: 1. WHEN CLKDBL IS DISABLED, ANY SPECIFICATION TO CLKIN APPLIES TO THE RISING EDGE, ONLY. 2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN APPLIES TO THE RISING OR FALLING EDGE.
2
tCKOP2 tCKWL2
SUGGESTED COMPONENTS FOR 100MHz OPERATION: ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE) ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE) C1 = 27pF C2 = 27pF NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1. CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.
Figure 14. Clock Input Clock Signals Figure 15. 100 MHz Operation (Fundamental Mode Crystal)
The ADSP-21161N can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21161N to use its internal clock generator by connecting
-24-
REV. A
ADSP-21161N
Reset Table 11. Reset Parameter Min Max Unit
Timing Requirements RESET Pulsewidth Low1 tWRST tSRST RESET Setup Before CLKIN High2
1 2
4tCK 8.5
ns ns
Applies after the power-up sequence is complete. Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21161Ns communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
tWRST
RESET
tSRST
Figure 16. Reset Interrupts Table 12. Interrupts Parameter Min Max Unit
Timing Requirements tSIR IRQ2-0 Setup Before CLKIN1 tHIR IRQ2-0 Hold After CLKIN1 tIPW IRQ2-0 Pulsewidth2
1 2
6 0 2 + tCKOP
ns ns ns
Only required for IRQx recognition in the following cycle. Applies only if tSIR and tHIR requirements are not met.
CLKIN
tSIR
tHIR
IRQ2-0
tIPW
Figure 17. Interrupts
REV. A
-25-
ADSP-21161N
Timer Table 13. Timer Parameter Min Max Unit
Switching Characteristic tDTEX CLKIN to TIMEXP
1
7
ns
CLKIN
tDTEX
TIMEXP
tDTEX
Figure 18. Timer Flags Table 14. Flags Parameter Min Max Unit
Timing Requirement FLAG11-0IN Setup Before CLKIN1 tSFI tHFI FLAG11-0IN Hold After CLKIN1 tDWRFI FLAG11-0IN Delay After RD/WR Low1 tHFIWR FLAG11-0IN Hold After RD/WR Deasserted1 Switching Characteristics tDFO FLAG11-0OUT Delay After CLKIN tHFO FLAG11-0OUT Hold After CLKIN CLKIN to FLAG11-0OUT Enable tDFOE tDFOD CLKIN to FLAG11-0OUT Disable
1
4 1 12 0 9 1 1 5
ns ns ns ns ns ns ns ns
Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
CLKIN
tDFOE
tDFO tHFO
tDFO
tDFOD
FLAG11-0OUT FLAG OUTPUT
CLKIN
tSFI
FLAG11-0IN
tHFI
tDWRFI
RD, WR FLAG INPUT
tHFIWR
Figure 19. Flags
-26-
REV. A
ADSP-21161N
Memory Read - Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchronous access mode.
Table 15. Memory Read - Bus Master Parameter Min Max Unit
Timing Requirements tDAD Address, Selects Delay to Data Valid1, 2 tDRLD RD Low to Data Valid1 tHDA Data Hold from Address, Selects3 tSDS Data Setup to RD High tHDRH Data Hold from RD High3 tDAAK ACK Delay from Address, Selects2, 4 tDSAK ACK Delay from RD Low4 tSAKC ACK Setup to CLKIN4 tHAKC ACK Hold After CLKIN
0 8 1
0.5tCCLK+3 1
tCKOP -0.25tCCLK -11+W ns 0.75tCKOP -11+W ns ns ns ns tCKOP -0.5tCCLK -12+W ns tCKOP -0.75tCCLK -11+W ns ns ns
Switching Characteristics tDRHA Address Selects Hold After RD High 0.25tCCLK-1+H ns tDARL Address Selects to RD Low2 0.25tCCLK -3 ns tRW RD Pulsewidth tCKOP-0.5tCCLK -1+W ns tRWR RD High to WR, RD, DMAGx Low 0.5tCCLK -1+HI ns W = (number of wait states specified in WAIT register) x tCKOP. HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). H = tCKOP (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1 2
Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS. The falling edge of MSx, BMS is referenced. 3 Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on Page 51 for the calculation of hold times given capacitive and dc loads. 4 ACK Delay/Setup: User must meet tDAAK, tDSAK, or tSAKC for deassertion of ACK (Low); all three specifications must be met for assertion of ACK (High).
tHDA
ADDRESS MSx, BMS
tDARL
RD
tRW
tDRHA
tDRLD tDAD
DATA
tSDS tHDRH
tDSAK tDAAK
ACK
tRWR
tSAKC
CLKIN
tHAKC
WR, DMAG
Figure 20. Memory Read - Bus Master
REV. A
-27-
ADSP-21161N
Memory Write - Bus Master
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-21161N is the bus master accessing external memory space in asynchronous access mode.
Table 16. Memory Write - Bus Master Parameter Min Max Unit
Timing Requirements ACK Delay from Address, Selects1, 2 tDAAK tDSAK ACK Delay from WR Low1 ACK Setup to CLKIN1 tSAKC tHAKC ACK Hold After CLKIN1
tCKOP-0.5tCCLK-12+W tCKOP-0.75tCCLK-11+W 0.5tCCLK +3 1
ns ns ns ns
Switching Characteristics tDAWH Address, Selects to WR Deasserted2 tCKOP - 0.25tCCLK - 3+W ns Address, Selects to WR Low2 0.25tCCLK - 3 ns tDAWL tWW WR Pulsewidth tCKOP - 0.5tCCLK - 1+W ns tDDWH Data Setup Before WR High tCKOP -0.25tCCLK - 13.5+W ns tDWHA Address Hold After WR Deasserted 0.25tCCLK - 1+H ns tDWHD Data Hold After WR Deasserted 0.25tCCLK - 1+H ns tDATRWH Data Disable After WR Deasserted3 0.25tCCLK - 2+H 0.25tCCLK+2.5+H ns WR High to WR, RD, DMAGx Low 0.5tCCLK - 1.25+HI ns tWWR tDDWR Data Disable Before WR or RD Low 0.25tCCLK - 3+I ns tWDE WR Low to Data Enabled -0.25tCCLK - 1 ns W = (number of wait states specified in WAIT register) x tCKOP. H = tCKOP (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0). HI = tCKOP (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0). I = tCKOP (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1 2
ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low); all three specifications must be met for assertion of ACK (High). The falling edge of MSx, BMS is referenced. 3 See Example System Hold Time Calculation on Page 51 for calculation of hold times given capacitive and dc loads.
ADDRESS MSx, BMS
tDAWH tDAWL
WR
tDWHA tWW
tWWR tWDE tDDWH tDATRWH tDDWR
DATA
tDSAK tDAAK
ACK
tDWHD
tSAKC
CLKIN
tHAKC
RD, DMAG
Figure 21. Memory Write - Bus Master
-28-
REV. A
ADSP-21161N
Synchronous Read/Write - Bus Master
Use these specifications for interfacing to external memory systems that require CLKIN, relative to timing or for accessing a slave ADSP-21161N (in multiprocessor memory space). When accessing a slave ADSP-21161N, these switching characteristics
Table 17. Synchronous Read/Write - Bus Master Parameter
must meet the slave's timing requirements for synchronous read/writes (see Synchronous Read/Write - Bus Slave on Page 30). The slave ADSP-21161N must also meet these (bus master) timing requirements for data and acknowledge setup and hold times.
Min
Max
Unit
Timing Requirements Data Setup Before CLKIN tSSDATI tHSDATI Data Hold After CLKIN tSACKC ACK Setup Before CLKIN tHACKC ACK Hold After CLKIN Switching Characteristics tDADDO Address, MSx, BMS, BRST, Delay After CLKIN tHADDO Address, MSx, BMS, BRST, Hold After CLKIN RD High Delay After CLKIN tDRDO tDWRO WR High Delay After CLKIN tDRWL RD/WR Low Delay After CLKIN tDDATO Data Delay After CLKIN tHDATO Data Hold After CLKIN
5.5 1 0.5tCCLK+3 1 10 1.5 0.25tCCLK-1 0.25tCCLK-1 0.25tCCLK-1 1.5 0.25tCCLK+9 0.25tCCLK+9 0.25tCCLK+9 12.5
ns ns ns ns ns ns ns ns ns ns ns
CLKIN
tDADDO
ADDRESS MSx, BRST
tHADDO
tSACKC
ACK (IN)
tHACKC
READ CYCLE
tDRWL
RD
tDRDO
tSSDATI
DATA (IN)
tHSDATI
WRITE CYCLE
tDRWL
WR
tDWRO
tDDATO
DATA (OUT)
tHDATO
Figure 22. Synchronous Read/Write - Bus Master
REV. A
-29-
ADSP-21161N
Synchronous Read/Write - Bus Slave
Use these specifications for ADSP-21161N bus master accesses of a slave's IOP registers in multiprocessor memory space. The bus master must meet these (bus slave) timing requirements.
Table 18. Synchronous Read/Write - Bus Slave Parameter Min Max Unit
Timing Requirements tSADDI Address, BRST Setup Before CLKIN Address, BRST Hold After CLKIN tHADDI tSRWI RD/WR Setup Before CLKIN tHRWI RD/WR Hold After CLKIN Data Setup Before CLKIN tSSDATI Data Hold After CLKIN tHSDATI Switching Characteristics tDDATO Data Delay After CLKIN tHDATO Data Hold After CLKIN tDACKC ACK Delay After CLKIN ACK Hold After CLKIN tHACKO
5 1 5 1 5.5 1 12.5 1.5 10 1.5
ns ns ns ns ns ns ns ns ns ns
CLKIN
tSADDI
ADDRESS
tHADDI
tDACKC
ACK
tHACKO
READ ACCESS RD
tSRWI
tHRWI
tDDATO
DATA (OUT) WRITE ACCESS
tHDATO
tSRWI
tHRWI
WR
tSSDATI
DATA (IN)
tHSDATI
Figure 23. Synchronous Read/Write - Bus Slave
-30-
REV. A
ADSP-21161N
Host Bus Request
Use these specifications for asynchronous host bus requests of an ADSP-21161N (HBR, HBG).
Table 19. Host Bus Request Parameter Min Max Unit
Timing Requirements tHBGRCSV HBG Low to RD/WR/CS Valid tSHBRI HBR Setup Before CLKIN1 HBR Hold After CLKIN1 tHHBRI tSHBGI HBG Setup Before CLKIN tHHBGI HBG Hold After CLKIN
19 6 1 6 1 7 10 11
ns ns ns ns ns ns ns ns ns ns
Switching Characteristics tDHBGO HBG Delay After CLKIN tHHBGO HBG Hold After CLKIN 1.5 tDRDYCS REDY (O/D) or (A/D) Low from CS and HBR Low2 REDY (O/D) Disable or REDY (A/D) High from HBG2 tCKOP+14 tTRDYHG tARDYTR REDY (A/D) Disable from CS or HBR High2
1 2
Only required for recognition in the current cycle. (O/D) = open drain, (A/D) = active drive.
CLKIN
tSH B R I
HBR
tH H BR I
tD H BG O tH H B GO
HBG (OUT)
tSH B GI
HBG (IN)
tH H B GI
HBR CS REDY (O/D)
tD R DY C S
tTR D YH G
tA R D YTR
REDY (A/D)
tH B GR CS V
HBG (OUT) RD WR CS O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 24. Host Bus Request
REV. A
-31-
ADSP-21161N
Multiprocessor Bus Request
Use these specifications for passing of bus mastership between multiprocessing ADSP-21161Ns (BRx).
Table 20. Multiprocessor Bus Request Parameter Min Max Unit
Timing Requirements BRx, Setup Before CLKIN High tSBRI tHBRI BRx, Hold After CLKIN High tSPAI PA Setup Before CLKIN High PA Hold After CLKIN High tHPAI tSRPBAI RPBA Setup Before CLKIN High tHRPBAI RPBA Hold After CLKIN High Switching Characteristics BRx Delay After CLKIN High tDBRO BRx Hold After CLKIN High tHBRO tDPASO PA Delay After CLKIN High, Slave tTRPAS PA Disable After CLKIN High, Slave tDPAMO PA Delay After CLKIN High, Master PA Disable Before CLKIN High, Master tPATR
9 0.5 9 1 6 2 8 1.0 8 1.5 0.25tCCLK+9 0.25tCCLK-5
ns ns ns ns ns ns ns ns ns ns ns ns
CLKIN
tD B RO tH B RO
BRx (OUT)
t DP A SO
PA (OUT) (SLAVE)
tTR PA S
tD PA MO
PA (OUT) (MASTER)
tP AT R
tSB R I
BRx (IN)
tH BR I
tS PA I
PA (IN) (O/D)
tH PA I
tS R PB A I
RPBA
t HR P B AI
O/D = OPEN DRAIN
Figure 25. Multiprocessor Bus Request
-32-
REV. A
ADSP-21161N
Asynchronous Read/Write - Host to ADSP-21161N
Use these specifications for asynchronous host processor accesses of an ADSP-21161N, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-21161N, the host can drive the RD and WR pins to access the ADSP-21161N's IOP registers. HBR and HBG are assumed low for this timing.
Table 21. Read Cycle Parameter
Although the DSP will recognize HBR asserted before reset, a HBG will not be returned by the DSP until after reset is deasserted and the DSP completes bus synchronization. Note: Host internal memory access is not supported.
Min
Max
Unit
Timing Requirements tSADRDL Address Setup and CS Low Before RD Low tHADRDH Address Hold and CS Hold Low After RD RD/WR High Width tWRWH tDRDHRDY RD High Delay After REDY (O/D) Disable tDRDHRDY RD High Delay After REDY (A/D) Disable Switching Characteristics tSDATRDY Data Valid Before REDY Disable from Low tDRDYRDL REDY (O/D) or (A/D) Low Delay After RD Low tRDYPRD REDY (O/D) or (A/D) Low Pulsewidth for Read Data Disable After RD High tHDARWH
Table 22. Write Cycle Parameter
0 2 3.5 0 0 2 10 1.5tCCLK 2 6
ns ns ns ns ns ns ns ns ns
Min
Max
Unit
Timing Requirements tSCSWRL CS Low Setup Before WR Low tHCSWRH CS Low Hold After WR High tSADWRH Address Setup Before WR High Address Hold After WR High tHADWRH tWWRL WR Low Width tWRWH RD/WR High Width tDWRHRDY WR High Delay After REDY (O/D) or (A/D) Disable tSDATWH Data Setup Before WR High tHDATWH Data Hold After WR High Switching Characteristics REDY (O/D) or (A/D) Low Delay After WR/CS Low1 tDRDYWRL REDY (O/D) or (A/D) Low Pulsewidth for Write1 tRDYPWR
1
0 0 6 2 tCCLK+1 3.5 0 5 4 11 12
ns ns ns ns ns ns ns ns ns ns ns
Only when slave write FIFO is full.
REV. A
-33-
ADSP-21161N
READ CYCLE
ADDRESS/CS
tSADRDL
tHADRDH tWRWH
RD
tHDARW H
DATA (OUT)
tS DAT RDY tDRDY RDL
REDY (O/D)
tDRDHRDY tRDYPRD
REDY (A/D)
WRITE CYCLE
ADDRESS
tS ADW RH tSCS WRL
CS
tHADW RH tHCSWRH
t WWRL
WR
tW RW H
tSDATWH
DATA (IN)
tHDATWH
tDRDY WRL
REDY (O/D)
tRDYPW R
tDWRHRDY
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 26. Asynchronous Read/Write - Host to ADSP-21161N
-34-
REV. A
ADSP-21161N
Three-State Timing - Bus Master, Bus Slave
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Table 23. Three-State Timing - Bus Master, Bus Slave Parameter
During reset, the DSP will not respond to SBTS, HBR, and MMS accesses. Although the DSP will recognize HBR asserted before reset, a HBG will not be returned by the DSP until after reset is deasserted and the DSP completes bus synchronization.
Min
Max
Unit
Timing Requirements tSTSCK SBTS Setup Before CLKIN tHTSCK SBTS Hold After CLKIN Switching Characteristics Address/Select Enable After CLKIN High tMIENA tMIENS Strobes Enable After CLKIN High1 tMIENHG HBG Enable After CLKIN tMITRA Address/Select Disable After CLKIN High tMITRS Strobes Disable After CLKIN High tMITRHG HBG Disable After CLKIN2 Data Enable After CLKIN3 tDATEN tDATTR Data Disable After CLKIN3 tACKEN ACK Enable After CLKIN High tACKTR ACK Disable After CLKIN High tCDCEN CLKOUT Enable After CLKIN2 tCDCTR CLKOUT Disable After CLKIN Address/Select Disable Before HBG Low4 tATRHBG tSTRHBG RD/WR/DMAGx Disable Before HBG Low4 tBTRHBG BMS Disable Before HBG Low4 tMENHBG Memory Interface Enable After HBG High4
1 2
6 2 1.5 -1.5 1.5 -0.5tCKOP-20 tCKOP- 0.25tCCLK-17 0.5tCKOP+NxtCCLK-20 1.5 1.5 1.5 0.2 0.5tCKOP+NxtCCLK tCKOP-5 1.5tCKOP-6 tCKOP+ 0.25tCCLK-4 0.5tCKOP-4 tCKOP-5 9 +9 9 -0.5tCKOP-15 tCKOP- 0.25tCCLK-12.5 0.5tCKOP+NxtCCLK-15 10 6 9 5 0.5tCKOP+NxtCCLK+5 tCKOP 1.5tCKOP+2 tCKOP+ 0.25tCCLK+3 0.5tCKOP+2 tCKOP+5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Strobes = RD, WR, DMAGx. Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively. 3 In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. 4 Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.
REV. A
-35-
ADSP-21161N
CLKIN
tSTSCK tHTSCK
SBTS
tMIENA, tMIENS, tMIENHG
MEMORY INTERFACE
tMITRA, tMITRS, tMITRHG
tDATEN
DATA
tDATTR
tACKEN
ACK
tACKTR
CLKIN
tCDCEN
CLKOUT
tCDCTR
HBG
tMENHBG
MEMORY INTERFACE MEMORY INTERFACE = ADDRESS, RD, WR, MSx, DMAGx, BMS (IN EPROM MODE)
tATRHBG, tSTRHBG, tBTRHBG
Figure 27. Three-State Timing - Bus Master, Bus Slave
-36-
REV. A
ADSP-21161N
DMA Handshake
These specifications describe the three DMA handshake modes. In all three modes DMAR is used to initiate transfers. For handshake mode, DMAG controls the latching or enabling of data externally. For external handshake mode, the data transfer is controlled by the ADDR23-0, RD, WR, MS3-0, ACK, and
Table 24. DMA Handshake Parameter
DMAG signals. For Paced Master mode, the data transfer is controlled by ADDR23-0, RD, WR, MS3-0, and ACK (not DMAG). For Paced Master mode, the Memory Read-Bus Master, Memory Write-Bus Master, and Synchronous Read/Write-Bus Master timing specifications for ADDR23-0, RD, WR, MS3-0, DATA47-16, and ACK also apply.
Min
Max
Unit
Timing Requirements tSDRC DMARx Setup Before CLKIN1 tWDR DMARx Width Low (Nonsynchronous)2 tSDATDGL Data Setup After DMAGx Low3 tHDATIDG Data Hold After DMAGx High Data Valid After DMARx High3 tDATDRH tDMARLL DMARx Low Edge to Low Edge4 tDMARH DMARx Width High2
3.5 tCCLK +4.5 tCKOP - 0.5tCCLK -7 2 tCKOP +3 tCKOP tCCLK +4.5 0.25tCCLK +9
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching Characteristics tDDGL DMAGx Low Delay After CLKIN 0.25tCCLK +1 tWDGH DMAGx High Width 0.5tCCLK - 1+HI tWDGL DMAGx Low Width tCKOP - 0.5tCCLK - 1 DMAGx High Delay After CLKIN tCKOP - 0.25tCCLK +1.0 tHDGC tVDATDGH Data Valid Before DMAGx High5 tCKOP - 0.25tCCLK - 8 tDATRDGH Data Disable After DMAGx High6 0.25tCCLK - 3 tDGWRL WRx Low Before DMAGx Low -1.5 tDGWRH DMAGx Low Before WRx High tCKOP - 0.5tCCLK - 2 +W tDGWRR WRx High Before DMAGx High7 -1.5 RDx Low Before DMAGx Low -1.5 tDGRDL tDRDGH RDx Low Before DMAGx High tCKOP - 0.5tCCLK -2+W tDGRDR RDx High Before DMAGx High7 -1.5 tDGWR DMAGx High to WRx, RDx Low 0.5tCCLK - 2+HI tDADGH Address/Select Valid to DMAGx High 15 tDDGHA Address/Select Hold After DMAGx High 1 W = (number of wait states specified in WAIT register) x tCKOP. HI = tCKOP (if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1 2
tCKOP - 0.25tCCLK +9 tCKOP - 0.25tCCLK +5 0.25tCCLK +4 +2 +2 +2 +2
Only required for recognition in the current cycle. Maximum throughput using DMARx/DMAGx handshaking equals tWDR + tDMARH = (tCCLK +4.5) + (tCCLK +4.5)=29 ns (34.5 MHz). This throughput limit applies to non-synchronous access mode only. 3 tSDATDGL is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of the write, the data can be driven tDATDRH after DMARx is brought high. 4 Use tDMARLL if DMARx transitions synchronous with CLKIN. Otherwise, use tWDR and tDMARH. 5 tVDATDGH is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then tVDATDGH = tCKOP - 0.25tCCLK - 8 + (n x tCKOP) where n equals the number of extra cycles that the access is prolonged. 6 See Example System Hold Time Calculation on Page 51 for calculation of hold times given capacitive and dc loads. 7 This parameter applies for synchronous access mode only.
REV. A
-37-
ADSP-21161N
CLKIN
tDMARLL tSDRC tWDR
DMARx
tSDRC tDMARH
tHDGC tDDGL
DMAGx
tWDGL
tWDGH
TRANSFERS BETWEEN ADSP-21161N INTERNAL MEMORY AND EXTERNAL DEVICE
tVDATDGH
tDATRDGH
DATA (FROM ADSP-2116x TO EXTERNAL DRIVE)
tDATDRH tSDATDGL
DATA (FROM EXTERNAL DRIVE TO ADSP-21161N)
tHDATIDG
TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY1 (EXTERNAL HANDSHAKE MODE)
tDGWRL
WR (EXTERNAL DEVICE TO EXTERNAL MEMORY)
tDGWRH
tDGWRR
tDGWR
tDGRDL
RD (EXTERNAL MEMORY TO EXTERNAL DEVICE)
tDGRDR
tDRDGH tDADGH
ADDRESS MSx
1MEMORY
tDDGHA
READ BUS MASTER, MEMORY WRITE BUS MASTER, OR SYNCHRONOUS READ/WRITE BUS MASTER TIMING SPECIFICATIONS FOR ADDR23-0, RD, WR, MS3-0 AND ACK ALSO APPLY HERE.
Figure 28. DMA Handshake
-38-
REV. A
ADSP-21161N
SDRAM Interface - Bus Master
Use these specifications for ADSP-21161N bus master accesses of SDRAM:
Table 25. SDRAM Interface - Bus Master Parameter Min Max Unit
Timing Requirements Data Setup Before SDCLK tSDSDK tHDSDK Data Hold After SDCLK Switching Characteristics tDSDK1 First SDCLK Rise Delay After CLKIN1, 2 tSDK SDCLK Period tSDKH SDCLK Width High SDCLK Width Low tSDKL tDCADSDK Command, Address, Data, Delay After SDCLK3 tHCADSDK Command, Address, Data, Hold After SDCLK3 Data Three-State After SDCLK4 tSDTRSDK tSDENSDK Data Enable After SDCLK5 tSDCTR Command Three-State After CLKIN tSDCEN Command Enable After CLKIN tSDSDKTR SDCLK Three-State After CLKIN tSDSDKEN SDCLK Enable After CLKIN Address Three-State After CLKIN tSDATR tSDAEN Address Enable After CLKIN
1
2.0 2.3 0.75tCCLK + 1.5 tCCLK 4 4 0.75tCCLK + 8.0 2 x tCCLK
ns ns ns ns ns ns ns ns 0.5tCCLK + 2.0 ns ns ns ns ns ns ns ns
0.25tCCLK +2.5 2.0
0.75tCCLK 0.5tCCLK -1.5 2 0 1 -0.25 tCCLK-5 -0.4
0.5tCCLK + 6.0 5 3 4 -0.25tCCLK +7.2
For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the SDCKR value and the core clock to CLKIN ratio. 2 Subtract tCCLK from result if value is greater than or equal to tCCLK. 3 Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE 4 SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write. 5 Valid when DSP transitions to SDRAM master from SDRAM slave.
SDRAM Interface - Bus Slave
These timing requirements allow a bus slave to sample the bus master's SDRAM command and detect when a refresh occurs:
Table 26. SDRAM Interface - Bus Slave Parameter Min Max Unit
Timing Requirements First SDCLK Rise tSSDKC1 after CLKOUT1, 2, 3 Command Setup tSCSDK before SDCLK4 Command Hold tHCSDK after SDCLK4
1
SDCK 2 1
tCCLK -0.5tCCLK- 0.5
SDCKR
tCCLK -0.25tCCLK + 2.0
ns ns ns
For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the tDSDK1 and tSSDKC1 values, depending upon the SDCKR value and the Core clock to CLKOUT ratio. 2 SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency. 3 Subtract tCCLK from result if value is greater than or equal to tCCLK. 4 Command = SDCKE, RAS, CAS, and SDWE.
REV. A
-39-
ADSP-21161N
CLKIN
tDSDK1
tSDK
tSDKH
SDCLK
tSDSDK tHDSDK
DATA(IN)
tSDKL
tDCADSDK tSDENSDK
DATA(OUT)
tSDTRSDK tHCADSDK
CMND1ADDR (OUT)
tDCADSDK
tSDCEN
CMND1(OUT)
tHCADSDK
tSDCTR
ADDR (OUT)
tSDAEN
tSDATR
CLKIN
tSDSDKEN
SDCLK
tSDSDKTR
CLKOUT
tSSDKC1
SDCLK (IN)
tSCSDK
CMND2 (IN)
tHCSDK
1COMMAND 2COMMAND
= SDCKE, MSx, RAS, CAS, SDWE, DQM, AND SDA10. = SDCKE, RAS, CAS, AND SDWE.
Figure 29. SDRAM Interface
-40-
REV. A
ADSP-21161N
Link Ports
Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path between LDATA and LCLK. Setup skew is the maximum delay that can be introduced in LDATA relative to LCLK, (setup skew = tLCLKTWH min- tDLDCH - tSLDCL). Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA, (hold skew = tLCLKTWL min - tHLDCH - tHLDCL). Calculations made directly from speed specifications
Table 27. Link Ports - Receive Parameter
will result in unrealistically small skew times because they include multiple tester guardbands. The setup and hold skew times shown below are calculated to include only one tester guardband. ADSP-21161N Setup Skew = 1.5 ns max ADSP-21161N Hold Skew = 1.5 ns max Note that there is a two-cycle effect latency between the link port enable instruction and the DSP enabling the link port.
Min
Max
Unit
Timing Requirements tSLDCL Data Setup Before LCLK Low tHLDCL Data Hold After LCLK Low LCLK Period tLCLKIW tLCLKRWL LCLK Width Low tLCLKRWH LCLK Width High Switching Characteristics tDLALC LACK Low Delay After LCLK High1
1
1 3.5 tLCLK 4.0 4.0 8 12
ns ns ns ns ns ns
LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
RECEIVE
tLCLKIW tLCLKRWH
LCLK
tLCLKRWL
tSLDCL
LDAT7-0 IN
tHLDCL
tDLALC
LACK (OUT)
Figure 30. Link Ports--Receive
REV. A
-41-
ADSP-21161N
Table 28. Link Ports - Transmit Parameter Min Max Unit
Timing Requirements tSLACH LACK Setup Before LCLK High tHLACH LACK Hold After LCLK High Switching Characteristics Data Delay After LCLK High tDLDCH tHLDCH Data Hold After LCLK High tLCLKTWL LCLK Width Low tLCLKTWH LCLK Width High tDLACLK LCLK Low Delay After LACK High
8 -2 3 0 0.5tLCLK-1.0 0.5tLCLK-1.0 0.5tLCLK+3 0.5tLCLK+1.0 0.5tLCLK+1.0 3tLCLK+11
ns ns ns ns ns ns ns
TRANSMIT
tLCLKTWH
LCLK
tLCLKTWL
LAST NIBBLE/BYTE TRANSMITTED
FIRST NIBBLE/BYTE TRANSMITTED
LCLK INACTIVE (HIGH)
tDLDCH tHLDCH
LDAT7-0 OUT
tSLACH
LACK (IN)
tHLACH
tDLACLK
THE tSLACH REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
Figure 31. Link Ports--Transmit
-42-
REV. A
ADSP-21161N
Serial Ports
To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold, 2) data delay and data setup and hold, and 3) SCLK width.
Table 29. Serial Ports - External Clock Parameter Min Max Unit
Timing Requirements tSFSE Transmit/Receive FS Setup Before Transmit/Receive SCLK1 Transmit/Receive FS Hold After Transmit/Receive tHFSE SCLK1 Receive Data Setup Before Receive SCLK1 tSDRE Receive Data Hold After Receive SCLK1 tHDRE tSCLKW SCLKx Width tSCLK SCLKx Period
1
3.5 4 1.5 4 7 2tCCLK
ns ns ns ns ns ns
Referenced to sample edge.
Table 30. Serial Ports - Internal Clock Parameter Min Max Unit
Timing Requirements tSFSI FS Setup Time Before SCLK (Transmit/Receive Mode)1 FS Hold After SCLK (Transmit/Receive Mode)1 tHFSI tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1
1
8 0.5tCCLK+1 4 3
ns ns ns ns
Referenced to sample edge.
Table 31. Serial Ports - External Clock Parameter Min Max Unit
Switching Characteristics tDFSE FS Delay After SCLK (Internally Generated FS) 1, 2, 3 FS Hold After SCLK (Internally Generated FS)1, 2 , 3 tHOFSE tDDTE Transmit Data Delay After SCLK 1, 2 Transmit Data Hold After SCLK 1, 2 tHDTE
1 2
13 3 16 0
ns ns ns ns
Referenced to drive edge. SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register. 3 SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
Table 32. Serial Ports - Internal Clock Parameter Min Max Unit
Switching Characteristics tDFSI FS Delay After SCLK (Internally Generated FS)1, 2, 3 tHOFSI FS Hold After SCLK (Internally Generated FS)1, 2, 3 Transmit Data Delay After SCLK1, 2 tDDTI tHDTI Transmit Data Hold After SCLK1, 2 SCLK Width2 tSCLKIW
1 2
4.5 -1.5 7.5 0 0.5tSCLK-2.5 0.5tSCLK+2
ns ns ns ns ns
Referenced to drive edge. SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register. 3 SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
REV. A
-43-
ADSP-21161N
Table 33. Serial Ports - Enable and Three-State Parameter Min Max Unit
Switching Characteristics Data Enable from External Transmit SCLK1, 2 tDDTEN tDDTTE Data Disable from External Transmit SCLK1 tDDTIN Data Enable from Internal Transmit SCLK1 tDDTTI Data Disable from Internal Transmit SCLK1
1 2
4 10 0 3
ns ns ns ns
Referenced to drive edge. SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
Table 34. Serial Ports - External Late Frame Sync Parameter Min Max Unit
Switching Characteristics tDDTLFSE Data Delay from Late External Transmit FS or External Receive FS with MCE = 1, MFD = 01 Data Enable from Late FS or MCE = 1, MFD = 01 tDDTENFS
1
13 0.5
ns ns
MCE = 1, Transmit FS enable and Transmit FS valid follow tDDTLFSE and tDDTENFS.
-44-
REV. A
ADSP-21161N
DATA RECEIVE-- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DATA RECEIVE-- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
SCLK SCLK
tSCLKW
tDFSI tHOFSI
FS
tDFSE tSFSI tHFSI
FS
tHOFSE
tSFSE
tHFSE
tSDRI
DXA/DXB
tHDRI
DXA/DXB
tSDRE
tHDRE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT -- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT -- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
SCLK SCLK
tSCLKW
tDFSI tHOFSI
FS
tDFSE tSFSI tHFSI
FS
tHOFSE
tSFSE
tHFSE
tHDTI
DXA/DXB
tDDTI
DXA/DXB
tHDTE
tDDTE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL), SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE EDGE SCLK (EXT) SCLK
DRIVE EDGE
tDDTEN
DXA/DXB DRIVE EDGE SCLK (INT) SCLK
tDDTTE
DRIVE EDGE
tDDTIN
DXA/DXB
tDDTTI
Figure 32. Serial Ports
REV. A
-45-
ADSP-21161N
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0 DRIVE SCLK SAMPLE DRIVE
tSFSE/I
FS
tHOFSE/I
tDDTE/I tDDTENFS
DXA/DXB
tHDTE/I
1ST BIT 2ND BIT
tDDTLFSE
LATE EXTERNAL TRANSMIT FS
DRIVE SCLK
SAMPLE
DRIVE
tSFSE/I
FS
tHOFSE/I
tDDTE/I tDDTENFS
DXA/DXB
tHDTE/I
1ST BIT 2ND BIT
tDDTLFSE
Figure 33. Serial Ports - External Late Frame Sync
-46-
REV. A
ADSP-21161N
SPI Interface Specifications Table 35. SPI Interface Protocol - Master Switching and Timing Parameter Min Max Unit
Timing Requirements Data Input Valid to SPICLK Edge (Data Input Set-up tSSPIDM Time) SPICLK Last Sampling Edge to Data Input Not Valid tHSPIDM tSPITDM Sequential Transfer Delay Switching Characteristics Serial Clock Cycle tSPICLKM Serial Clock High Period tSPICHM tSPICLM Serial Clock Low Period tDDSPIDM SPICLK Edge to Data Out Valid (Data Out Delay Time) tHDSPIDM SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tSDSCIM_0 FLAG3-0 (SPI Device Select) Low to First SPICLK Edge for CPHASE = 0 FLAG3-0 (SPI Device Select) Low to First SPICLK Edge tSDSCIM_1 for CPHASE = 1 Last SPICLK Edge to FLAG3-0 High tHDSM
Table 36. SPI Interface Protocol - Slave Switching and Timing Parameter Min
0.5tCCLK+10 0.5tCCLK+1 2tCCLK 8 tCCLK 4tCCLK-4 4tCCLK-4 3 0 5tCCLK 3tCCLK tCCLK-3
ns ns ns ns ns ns ns ns ns ns ns
Max
Unit
Timing Requirements tSPICLKS Serial Clock Cycle tSPICHS Serial Clock High Period tSPICLS Serial Clock Low Period tSDSCO SPIDS Assertion to First SPICLK Edge CPHASE = 0 CPHASE = 1 tHDS Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0 Data Input Valid to SPICLK Edge (Data Input Set-up Time) tSSPIDS SPICLK Last Sampling Edge to Data Input Not Valid tHSPIDS SPIDS Deassertion Pulsewidth (CPHASE = 0) tSDPPW Switching Characteristics tDSOE SPIDS Assertion to Data Out Active tDSDHI SPIDS Deassertion to Data High Impedance SPICLK Edge to Data Out Valid (Data Out Delay Time) tDDSPIDS tHDSPIDS1 SPICLK Edge to Data Out Not Valid (Data Out Hold Time) tHDLSBS1 SPICLK Edge to Last Bit Out Not Valid (Data Out Hold Time) for LSB SPIDS Assertion to Data Out Valid (CPHASE = 0) tDSOV2
1 2
8tCCLK 4tCCLK-4 4tCCLK-4 3.5tCCLK+8 1.5tCCLK+8 0 0 tCCLK+1 tCCLK 2 1.5 0.25tCCLK+3 0.5tSPICLK+4.5tCCLK 1.5tCCLK+7 0.5tCCLK+5.5 0.5tCCLK+5.5 0.75tCCLK+3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
When CPHASE = 0 and baud rate is greater than 1, tHDLSBS affects the length of the last bit transmitted. Applies to the first deassertion of SPIDS only.
REV. A
-47-
ADSP-21161N
FL AG3- 0 (O UTPUT )
tSDSCIM
SPICLK (C P = 0) (O UTPUT )
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPITDM
tSPICLM
SPIC LK (CP = 1) (O UTPUT )
tSPICHM
t D D S P ID M
tHDSPIDM
MOSI (OUTPUT) CPHASE = 1 MI SO (INPUT)
MSB
LSB
t S S P ID M
MSB VALID
tHSSPIDM
t S S P ID M tHSPIDM
L SB VA LID
tD D S P I D M
MOSI (OUTPUT) CPHASE = 0 MI SO (INPUT) MSB
t H D SP I D M
L SB
tSSPIDM
MSB VAL ID
tHSPIDM
L SB VALID
Figure 34. SPI Interface Protocol - Master Switching and Timing
-48-
REV. A
ADSP-21161N
SPIDS (INPUT)
tSPICHS
SPICLK (CP = 0) (INPUT)
tSPICLS
tS P I C L K S
tHDS
tSDPPW
tSDSCO
SPICLK (CP = 1) (INPUT)
t S P IC LS
tS P I C H S
tDDSPIDS tDSO E
MISO (OUTPUT ) CPH ASE = 1 MOSI (IN PUT)
tHDSPIDS
MSB
tD D S P I D S
tDSDHI
L SB
tSSPIDS
MSB VA LID
tHSPIDS
tSSPIDS
L SB VA LID
t H S P ID S
tDSO V tDSO E
MISO (OUTPUT ) CPH ASE = 0 MOSI (IN PUT) MSB
t D D S P ID S
tHDLSBS
LSB
tDSDHI
t S SP I D S
MSB VALI D L SB VA LID
tH S P I D S
Figure 35. SPI Interface Protocol - Slave Switching and Timing
REV. A
-49-
ADSP-21161N
JTAG Test Access Port and Emulation Table 37. JTAG Test Access Port and Emulation Parameter Min Max Unit
Timing Requirements tTCK TCK Period TDI, TMS Setup Before TCK High tSTAP tHTAP TDI, TMS Hold After TCK High tSSYS System Inputs Setup Before TCK Low1 System Inputs Hold After TCK Low1 tHSYS tTRSTW TRST Pulsewidth Switching Characteristics tDTDO TDO Delay from TCK Low tDSYS System Outputs Delay After TCK Low2
1
tCK 5 6 2 15 4tCK 13 30
ns ns ns ns ns ns ns ns
System Inputs = DATA47-16, ADDR23-0, RD, WR, ACK, RPBA, SPIDS, EBOOT, LBOOT, DMAR2-1, CLK_CFG1-0, CLKDBL, CS, HBR, SBTS, ID2-0, IRQ2-0, RESET, BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, SDWE, HBG, RAS, CAS, SDCLK0, SDCKE, BRST, BR6-1, PA, MS3-0, FLAG11-0. 2 System Outputs = BMS, MISO, MOSI, SPICLK, DxA, DxB, SCLKx, FSx, LxDAT7-0, LxCLK, LxACK, DATA47-16, SDWE, ACK, HBG, RAS, CAS, SDCLK1-0, SDCKE, BRST, RD, WR, BR6-1, PA, MS3-0, ADDR23-0, FLAG11-0, DMAG2-1, DQM, REDY, CLKOUT, SDA10, TIMEXP, EMU, BMSTR, RSTOUT.
tTCK
TCK
tSTAP
TMS TDI
tHTAP
tDTDO
TDO
tSSYS
SYSTEM INPUTS
tHSYS
tDSYS
SYSTEM OUTPUTS
Figure 36. JTAG Test Access Port and Emulation
-50-
REV. A
ADSP-21161N
Output Drive Currents
Figure 37 shows typical I-V characteristics for the output drivers of the ADSP-21161N. The curves represent the current drive capability of the output drivers as a function of output voltage.
REFERENCE SIGNAL
tMEASURED tDIS
80 60 VDDEXT = 3.47V, -40C 50 40 30
LOAD (VDDEXT) CURRENT - mA
tENA
VOH (MEASURED) - VOL (MEASURED) + V V VOH 2.0V (MEASURED) 1.0V VOL (MEASURED)
VOH (MEASURED) VOL (MEASURED)
VDDEXT = 3.3V, +25C
tDECAY
VDDEXT = 3.13V, +105C
20 10 0 -10 -20 -30 -40 -50 -60 -80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 SWEEP (VDDEXT) VOLTAGE - V VDDEXT = 3.47V, -40C VDDEXT = 3.3V, +25C VDDEXT = 3.13V, +105C
OUTPUT STOPS DRIVING
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V.
Figure 38. Output Enable/Disable
and the input threshold for the device requiring the hold time. A typical V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDATRWH for the write cycle).
Figure 37. Typical Drive Currents Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Enable Time
TO OUTPUT PIN
50 1.5V
Output pins are considered to be enabled when they have made a transition from a high impedance state to the point when they start driving. The output enable time tENA is the interval from the point when a reference signal reaches a high or low voltage level to the point when the output has reached a specified high or low trip point, as shown in the Output Enable/Disable diagram (Figure 38). If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Output Disable Time
30pF
Figure 39. 31Equivalent Device Loading for AC Measurements (Includes All Fixtures)
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by V is dependent on the capacitive load, CL and the load current, IL. This decay time can be approximated by the following equation:
( C L V ) t DECAY = -------------------IL
INPUT OR OUTPUT
1.5V
1.5V
Figure 40. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable)
The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 38. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system, first calculate tDECAY using the equation given above. Choose V to be the difference between the ADSP-21161N's output voltage REV. A -51-
ADSP-21161N
Capacitive Loading
25
OUTPUT DELAY OR HOLD - ns
20
15
10 Y = 0.0835X - 2.42 5
Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 39 on Page 51). Figure 41 shows graphically how output delays and holds vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see Output Disable Time on Page 51.) The graphs of Figure 41, Figure 42, and Figure 43 may not be linear outside the ranges shown for Typical Output Delay vs. Load Capacitance and Typical Output Rise Time (20% - 80%, V = Min) vs. Load Capacitance.
Environmental Conditions
NOMINAL
-5 0 30 60 90 120 150 LOAD CAPACITANCE - pF 180 210
The thermal characteristics in which the DSP is operating influence performance.
Thermal Characteristics
Figure 41. Typical Output Delay or Hold vs. Load Capacitance (at Max Case Temperature)
16.0 14.0
RISE AND FALL TIMES - ns (0.694V TO 2.77V, 20% TO 80%)
12.0 10.0 8.0 6.0 4.0 2.0 0 0
Y = 0.0743X + 1.5613 RISE TIME
The ADSP-21161N is packaged in a 225-ball Mini Ball Grid Array (MBGA). The ADSP-21161N is specified for a case temperature (TCASE). To ensure that the TCASE data sheet specification is not exceeded, a heatsink and/or an air flow source may be used. Use the center block of ground pins (MBGA balls: F6-10, G6-10, H6-10, J6-10, K6-10) to provide thermal pathways to the printed circuit board's ground plane. A heatsink should be attached to the ground plane (as close as possible to the thermal pathways) with a thermal adhesive.
T CASE = T AMB + ( PD x CA )
FALL TIME Y = 0.0414X + 2.0128
where: * TCASE = Case temperature (measured on top surface of package)
20
40
60 80 100 120 140 LOAD CAPACITANCE - pF
160
180
200
* PD = Power dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation). * CA = Value from Table 38. * JB= 8.0C/W
Table 38. Airflow Over Package Versus CA
Figure 42. Typical Output Rise/Fall Time (20% - 80%, VDDEXT = Max)
16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0 FALL TIME Y = 0.0417X + 1.8674 Y = 0.0773X + 1.4399 RISE TIME
1
Airflow (Linear Ft./Min.) CA (C/W)1 JC = 6.8C/W.
0 17.9
200 15.2
400 13.7
RISE AND FALL TIMES - ns (0.694V TO 2.77V, 20% TO 80%)
0
20
40
60 80 100 120 140 LOAD CAPACITANCE - pF
160
180
200
Figure 43. Typical Output Rise/Fall Time (20% - 80%, VDDEXT = Min)
-52-
REV. A
ADSP-21161N
225-BALL METRIC MBGA PIN CONFIGURATIONS Table 39. 225-Ball Metric MBGA Pin Assignments Pin Name PBGA Pin Number Pin Name PBGA Pin Number Pin Name PBGA Pin Number Pin Name PBGA Pin Number
NC BMSTR BMS SPIDS EBOOT LBOOT SCLK2 D3B L0DAT4 L0ACK L0DAT2 L1DAT6 L1CLK L1DAT2 NC FLAG10 RESET FLAG8 D0A VDDEXT VDDINT VDDEXT VDDINT VDDEXT VDDINT VDDEXT L0DAT0 DATA39 DATA43 DATA41 IRQ2 ID1 ID2 ID0 VDDEXT GND GND GND GND GND VDDEXT DATA26 DATA24 DATA25 DATA27
A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 E01 E02 E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 E13 E14 E15 J01 J02 J03 J04 J05 J06 J07 J08 J09 J10 J11 J12 J13 J14 J15
TRST TDI RPBA MOSI FS0 SCLK1 D2B D3A L0DAT7 L0CLK L0DAT1 L1DAT4 L1ACK L1DAT0 RSTOUT1 FLAG5 FLAG7 FLAG9 FLAG6 VDDINT GND GND GND GND GND VDDINT DATA37 DATA40 DATA38 DATA36 TIMEXP ADDR22 ADDR20 ADDR23 VDDINT GND GND GND GND GND VDDINT DATA22 DATA19 DATA21 DATA23
B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 F13 F14 F15 K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15
TMS EMU GND SPICLK D0B D1A D2A FS2 FS3 L0DAT6 L1DAT7 L1DAT3 L1DAT1 DATA45 DATA47 FLAG1 FLAG2 FLAG4 FLAG3 VDDEXT GND GND GND GND GND VDDEXT DATA34 DATA35 DATA33 DATA32 ADDR19 ADDR17 ADDR21 ADDR2 VDDEXT VDDINT VDDEXT VDDINT VDDEXT VDDINT VDDEXT CAS DATA20 DATA16 DATA18
C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 G13 G14 G15 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 L13 L14 L15
TDO TCK FLAG11 MISO SCLK0 D1B FS1 VDDINT SCLK3 L0DAT5 L0DAT3 L1DAT5 DATA42 DATA46 DATA44 FLAG0 IRQ0 VDDINT IRQ1 VDDINT GND GND GND GND GND VDDINT DATA29 DATA28 DATA30 DATA31 ADDR16 ADDR12 ADDR18 ADDR6 ADDR0 MS1 BR6 VDDEXT WR SDA10 RAS ACK DATA17 DMAG2 DMAG1
D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 H13 H14 H15 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 M13 M14 M15
REV. A
-53-
ADSP-21161N
Table 39. 225-Ball Metric MBGA Pin Assignments (continued) Pin Name PBGA Pin Number Pin Name PBGA Pin Number Pin Name PBGA Pin Number Pin Name PBGA Pin Number
ADDR14 ADDR15 ADDR10 ADDR5 ADDR1 MS0 BR5 BR2 BRST SDCKE CS CLK_CFG1 CLK_CFG0 AVDD DMAR1
1
N01 N02 N03 N04 N05 N06 N07 N08 N09 N10 N11 N12 N13 N14 N15
ADDR13 ADDR9 ADDR8 ADDR4 MS2 SBTS BR4 BR1 SDCLK1 SDCLK0 REDY CLKIN DQM AGND DMAR2
P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 P15
NC ADDR11 ADDR7 ADDR3 MS3 PA BR3 RD CLKOUT HBR HBG CLKDBL XTAL SDWE NC
R01 R02 R03 R04 R05 R06 R07 R08 R09 R10 R11 R12 R13 R14 R15
RSTOUT exists only for silicon revisions 1.2 and greater. Leave this pin unconnected for silicon revisions 0.3, 1.0, and 1.1.
14 15 13
12 11
10 9
8 7
6 5
4 3
2 1
A B C D E F G H J K L M N P R
KEY: VDDINT VDDEXT GND* AGND AVDD SIGNAL
*USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL
PATHWAYS TO YOUR PRINTED CIRCUIT BOARD GROUND PLANE
Figure 44. 225-Ball Metric MBGA Pin Assignments (Bottom View, Summary)
-54-
REV. A
ADSP-21161N
OUTLINE DIMENSIONS
The ADSP-21161N comes in a 17 mm x 17 mm, 225-ball MBGA package with 15 rows of balls.
225-Ball Mini-BGA (CA-225)
17.00 BSC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A1 BALL INDICATOR 17.00 BSC 14.00 BSC SQ
1.00 BSC
A B C D E F G H J K L M N P R
TOP VIEW DETAIL A
1.00 BSC (BALL PITCH) BOTTOM VIEW
1.85 MAX (SEE NOTE 1) 1.31 MAX (SEE NOTE 1) SEATING PLANE 0.30 MIN 0.70 0.20 MAX 0.60 0.50 (BALL DIAMETER)
DETAIL A NOTES: 1. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MO-192-AAF2, EXCEPT FOR HEIGHT AND THICKNESS DIMENSIONS NOTED. 2. ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.25 OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. 3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.10 OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.
ORDERING GUIDE Case Temperature Range On-Chip SRAM
Part Number1
Instruction Rate
Operating Voltage
ADSP-21161NKCA-100 ADSP-21161NCCA-100
1
0C to +85C -40C to +105C
100 MHz 100 MHz
1 M bit 1 M bit
1.8 int/3.3 ext V 1.8 int/3.3 ext V
These parts are packaged in a 225-ball Mini-Ball Grid Array (MBGA).
REV. A
-55-
ADSP-21161N Revision History
Location Page
5/03--Changed from Rev. 0 to Rev. A Changes to: KEY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 SIMD Computational Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Off-Chip Memory and Peripherals Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Host Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Phase-Locked Loop and Crystal Double Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Design-for-Emulation Circuit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory Read - Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory Write - Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Synchronous Read/Write - Bus Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Host BusRequest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Asynchronous Read/Write - Host to ADSP-21161N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Three-State Timing - Bus Master, Bus Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 -56- REV. A
ADSP-21161N
Location Page
Changes to: Table 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figure 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figure 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Changes to formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global
REV. A
-57-
-58-
-59-
-60-
C02935-0-5/03(A)

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